参数资料
型号: CDB5340
厂商: Cirrus Logic Inc
文件页数: 3/14页
文件大小: 0K
描述: BOARD EVAL FOR CS5340 STEREO ADC
标准包装: 1
ADC 的数量: 1
位数: 24
采样率(每秒): 192k
数据接口: 串行
在以下条件下的电源(标准): 180mW @ 5V
工作温度: -10°C ~ 70°C
已用 IC / 零件: CS5340
已供物品:
产品目录页面: 756 (CN2011-ZH PDF)
相关产品: CS5340-DZZR-ND - IC ADC AUD 101DB 200KHZ 16-TSSOP
CS5340-CZZR-ND - IC ADC AUD 101DB 200KHZ 16-TSSOP
598-1686-ND - IC ADC AUD 101DB 200KHZ 16-TSSOP
598-1081-5-ND - IC ADC AUD 101DB 200KHZ 16-TSSOP
其它名称: 598-1544
CDB5340
1. CDB5340 SYSTEM OVERVIEW
The CDB5340 evaluation board is an excellent means of quickly evaluating the CS5340. The
CS8406 digital audio interface transmitter provides an easy interface to digital audio signal ana-
lyzers including the majority of digital audio test equipment.
The CDB5340 schematic has been partitioned into 5 schematics shown in Figure 2 through
Figure 6 . Each partitioned schematic is represented in the system diagram shown in Figure 1 .
Notice that the system diagram also includes
the interconnections between the
partitioned schematics.
2. CS8406 DIGITAL AUDIO TRANSMITTER
The system generates and encodes standard S/PDIF data using a CS8406 Digital Audio Trans-
mitter (see Figure 5 ). The outputs of the CS8406 are RS422 compatible differential line drivers.
The CS8406 supports both Left Justified and I 2 S data formats, as determined by the DIP switch,
S2. A description of the CS8406 is included in the CS8406 datasheet.
3. INPUT/OUTPUT FOR CLOCKS AND DATA
The evaluation board has been designed to allow interfacing to external systems via the 10-pin
header, J11. The schematic for the clock/data input/output is shown in Figure 4 .
The CDB5340 allows some flexibility as to the generation of the clocks. When the CS5340 and
CS8406 are in slave mode, the SCLK and LRCK must be provided via the header, J11. MCLK
can be generated from the on-board oscillator, Y1 or provided via the header, J11 as determined
by the DIP switch, S2. The on-board oscillator is socketed to allow other frequency oscillators to
be used. Please note that the on-board oscillator must be removed if an external MCLK is pro-
vided through header J11.
4. POWER SUPPLY CIRCUITRY
Power is supplied to the evaluation board by four binding posts (VA/VD, VL, GND, +5V),
see Figure 6 . The VA/VD input supplies the VA and VD pins of the CS5340. VL supplies power
to the VL pin of the CS5340 and to the level shifter circuits. The +5V input supplies power to the
digital circuitry and the input amplifiers.
5. GROUNDING AND POWER SUPPLY DECOUPLING
The CS5340 requires careful attention to power supply and grounding arrangements to optimize
performance. Figure 3 details the power distribution used on this board. The decoupling capac-
itors are located as close to the CS5340 as possible. Extensive use of ground plane fill in the
evaluation board yields large reductions in radiated noise.
6. ANALOG INPUT FILTER
The CDB5340 implements a single-ended analog input buffer, as shown in Figure 2 . Note that
there is no attenuation or gain associated with the input buffer.
DS601DB1
3
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