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参数资料
| 型号： | CDB5364 |
| 厂商： | Cirrus Logic Inc |
| 文件页数： | 16/42页 |
| 文件大小： | 0K |
| 描述： | EVALUATION BOARD FOR CS5364 |
| 标准包装： | 1 |
| ADC 的数量： | 1 |
| 位数： | 24 |
| 采样率（每秒）： | 192k |
| 数据接口： | I²C，SPI? |
| 在以下条件下的电源（标准）： | 365mW @ 192kSPS |
| 工作温度： | -40°C ~ 85°C |
| 已用 IC / 零件： | CS5364 |
| 已供物品： | 板，CD |
| 相关产品： | CS5364-CQZR-ND - IC ADC 4CH 114DB 216KHZ 48-LQFP 598-1697-ND - IC ADC 4CH 114DB 216KHZ 48-LQFP 598-1088-ND - IC ADC 4CH 114DB 216KHZ 48-LQFP |
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DS625F4
23
CS5364
4.5.2
TDM Format
In TDM Mode, all four channels of audio data are serially clocked out during a single Frame Sync (FS) cy-
cle, as shown in Figure 12. The rising edge of FS signifies the start of a new TDM frame cycle. Each chan-
nel slot occupies 32 SCLK cycles, with the data left justified and with MSB first. TDM output data should be
latched on the rising edge of SCLK within time specified under ‘Serial Audio Interface - TDM Timing” section
on page 16. The TDM data output port resides on the SDOUT1 pin. The TDM output pin is complimentary
TDM data. All SDOUT pins will remain active during TDM Mode. Refer to Section 4.11 “Optimizing Perfor-
mance in TDM Mode” on page 29 for critical system design information.
Figure 12. TDM Format
4.5.3
Configuring Serial Audio Interface Format
The serial audio interface format of the data is controlled by the configuration of the DIF1 and DIF0 pins in
Stand-Alone Mode or by the DIF[1] and DIF[0] bits in the Global Mode Control Register in Control Port
Mode, as shown in Table 2.
Table 2. DIF1 and DIF0 Pin Settings
4.6
Speed Modes
4.6.1
Sample Rate Ranges
CS5364 supports sampling rates from 2 kHz to 21 kHz, divided into three ranges: 2 kHz - 54 kHz, 54 kHz -
108 kHz, and 108 kHz - 216 kHz. These sampling speed modes are called Single-Speed Mode (SSM),
Double-Speed Mode (DSM), and Quad-Speed Mode (QSM), respectively.
4.6.2
Using M1 and M0 to Set Sampling Parameters
The Master/Slave operation and the sample rate range are controlled through the settings of the M1 and
M0 pins in Stand-Alone Mode, or by the M[1] and M[0] bits in the Global Mode Control Register in Control
Port Mode, as shown in Table 3.
Table 3. M1 and M0 Settings
DIF1
DIF0
Mode
0
Left-Justified
01
IS
10
TDM
11
Reserved
M1
M0
Mode
Frequency Range
0
Single-Speed Master Mode (SSM)
2 kHz - 54 kHz
0
1
Double-Speed Master Mode (DSM)
54 kHz - 108 kHz
1
0
Quadruple-Speed Master Mode (QSM)
108 kHz - 216 kHz
1
Auto-Detected Speed Slave Mode
2 kHz - 216 kHz
SCLK
LSB
MSB
LSB
MSB
LSB
MSB
TDM OUT
Channel 1
Channel 4
Channel 2
Channel 3
32 clks
FS
LSB
MSB
LSB
MSB
Data
Zeroes
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