参数资料
| 型号： | CDB5560-2 |
| 厂商： | Cirrus Logic Inc |
| 文件页数： | 8/26页 |
| 文件大小： | 0K |
| 描述： | DEV BOARD FOR CS5560 W/SE INPUT |
| 标准包装： | 1 |
| 其它名称： | 598-1274 |
CDB5560
3.4
3.4.1
Digital Section
Hardware Configuration
The CDB5560 evaluation board hardware comes pre-configured so the only connection required between
it and a data acquisition system is the serial port connection.
The hardware setup is reconfigurable through the hardware control interface connectors. Configure the
evaluation board by setting the appropriate control line to the appropriate logic level.
Table 4. Hardware Configuration Signals
Function
Input Channel Select
Analog Input Buffers
Serial Port Mode
Data Ready Flag
Reset
Bipolar / Unipolar Mode
Sleep Mode
Serial Port Communication
Data Conversion Mode
Default Level
INPUT A = Selected (Low)
Buffers = Enabled (High)
Sync. Self Clock = Enabled (High)
Data Ready When Set (Low)
Reset = Inactive (High)
Bipolar = Enabled (High)
Sleep = Inactive (High)
Chip Select = Enabled (Low)
Continuous Conversion = Active (Low)
Label
MUX
BUFEN
SMODE
RDY
RST
BP / UP
SLEEP
CS
CONV
Connector
J6, Pin 16
J1
J6, Pin 12
J8, Pin 10
J6, Pin 6; S1
J6, Pin 2
J6, Pin 4
J8, Pin 2
J8, Pin 12
Test Point
J3, Pin 2
J3, Pin1
J3, Pin 3
J3, Pin 4
J3, Pin 6
J3, Pin 8
J3, Pin 9
E23
E21
3.4.2
SPI? Serial Port Communications
The CS5560 ADC communications port features an SPI? serial port. It can be configured for SSC mode
(Master) or SEC mode (Slave) mode as shown in Table 4. Test points are provided to monitor serial com-
munications.
Connections to the serial interface are made according to the following table.
Table 5. Serial Interface Connections
8
Function
Chip Select
Serial Data Input
Serial Data Output
Serial Clock
Label
CS
SDI
SDO
SCLK
Connector
J8, Pin 2
J8, Pin 4
J8, Pin 6
J8, Pin 8
Test Point
E23
E24
E25
E26
DS713DB4
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