参数资料
型号: CDCE906-706PROGEVM
厂商: Texas Instruments
文件页数: 11/19页
文件大小: 0K
描述: EVAL MOD PROGRAMABLE CDCE906/706
标准包装: 1
类型: 时钟同步器
适用于相关产品: CDCE906,CDCE706
所含物品: 完全组装的评估板
相关产品: CDCE906PWRG4-ND - IC 3-PLL SYNTH/MULT/DIV 20-TSSOP
296-26038-2-ND - IC 3-PLL SYNTH/MULT/DIV 20-TSSOP
CDCE906PWG4-ND - IC 3-PLL SYNTH/MULT/DIV 20-TSSOP
CDCE706PWRG4-ND - IC 3-PLL SYNTH/MULT/DIV 20-TSSOP
CDCE706PWR-ND - IC 3-PLL SYNTH/MULT/DIV 20-TSSOP
CDCE706PWG4-ND - IC 3-PLL SYNTH/MULT/DIV 20-TSSOP
296-20675-5-ND - IC 3-PLL SYNTH/MULT/DIV 20-TSSOP
296-20674-5-ND - IC 3-PLL SYNTH/MULT/DIV 20-TSSOP
其它名称: 296-30829
CDCE906-706PROGEVM-ND
www.ti.com
TI Pro-Clock?
Figure 4. Programming Assistant
The Programming Assistant starts with its own default setup. The default setup of the Programming
Assistant is different to the default setup of the CDCE906/CDCE706. This is why, the Programming
Assistant has a simple startup setup, which makes it easy to create a new user-defined setup. From this
default setup, different parameters can be edited to create a user setup. All dividers, the VCO frequency,
the SSC modulation frequency, the switch A/B settings, as well as the actual output frequency, and the
actual error of all outputs, are calculated by defining the following parameters:
signal source
fin
CDCE906/
CDCE706 Switch
SSC Modulation
fmod
fout
error
disable PLL
bypass
activate SSC
Choose among crystal oscillator, LVMOS, and differential clock source
Choose from 1 MHz to 167/200 MHz for CDCE906/CDCE706 LVCMOS/differential
input and from 8 MHz to 54 MHz for crystal oscillator
Choose if a CDCE706 or a CDCE906 setup is provided
Choose between no modulation and different center and down-spread modulations
provided by PLL 2
Choose a modulation frequency for SSC; actual fmod shows the closest possible
modulation frequency
Choose the output frequency for Y0–Y5; actual fout displays the closest possible
output frequency with an error in frequency smaller than |error|
Choose the maximum allowed error between fout and actual fout; actual error
displays the error of current frequency actual fout
If the input frequency is a multiple of fout, fout is derived directly from fin. Click
disable PLL bypass if Yx should be derived from a PLL.
Choose which outputs will have SSC. All outputs with SSC activated must be
derived from the same PLL.
SCAU017B – August 2006 – Revised August 2007
CDCE906/CDCE706 Programming Evaluation Module
11
相关PDF资料
PDF描述
395-056-540-204 CARD EDGE 56POS DL .100X.200 BLK
395-056-540-202 CARD EDGE 56POS DL .100X.200 BLK
RKZ-1212D/P CONV DC/DC 2W 12VIN +/-12VOUT
M7WWK-2510R D-SUB CABLE MFU25K/MC26M/MFU25K
395-056-542-204 CARD EDGE 56POS DL .100X.200 BLK
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