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参数资料
| 型号： | CH5101A-L |
| 厂商： | Electronic Theatre Controls, Inc. |
| 英文描述： | CMOS Monochrome Digital Video Camera |
| 中文描述： | 单色的CMOS数码摄像机 |
| 文件页数： | 13/32页 |
| 文件大小： | 132K |
| 代理商： | CH5101A-L |
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CHRONTEL
CH5101A
201-0000-033 Rev 1.0, 6/2/99
13
Figure 8
shows two consecutive alternating write cycles for AutoInc = 0 and R/W* = 0. The byte of information
following the Register Address Byte (RAB) is the data to be written into the register specified by AR[5:0]. If
AutoInc = 0, then another RAB is expected from the master device followed by another data byte, and so on.
Figure 8: Alternating Write Cycles
Note:
The acknowledge is from the CH5101 (slave).
If AutoInc = 1, then the register address pointer will be incremented automatically and subsequent data bytes will be
written into successive registers without providing an RAB between each data byte. An auto-increment write cycle
is shown in
Figure 9
.
Figure 9: Auto-Increment Write Cycle
Note:
The acknowledge is from the CH5101 (slave).
When the auto-increment mode is enabled (AutoInc is set to 1), the register address pointer continues to increment
for each write cycle until AR[5:0] = 26 (26 is the address of the address register). The next byte of information
represents a new auto-sequencing starting address which is the address of the register to receive the next byte. The
auto-sequencing then resumes based on this new starting address. The auto-increment sequence can be terminated
any time by either a STOP or RESTART condition. The write operation can be terminated with a STOP condition.
CH5101 Read Cycle Protocols (R/W = 1)
If a master-receiver is involved in a transfer, it must signal the end of data to the slave-transmitter by not generating
an acknowledge on the last byte that was clocked out of the slave. The slave-transmitter CH5101 releases the data
line to allow the master to generate the STOP condition or the RESTART condition.
To read the content of the registers, the master device starts by issuing a START condition (or a RESTART
condition). The first byte of data, after the START condition, is a DAB with R/W = 0. The second byte is the RAB
with AR[5:0] containing the address of the register that the master device intends to read from in AR[5:0]. The
master device should then issue a RESTART condition (RESTART = START, without a previous STOP condition).
The first byte of data, after this RESTART condition, is another DAB with R/W*=1, indicating the master’s
intention to read data hereafter. The master then reads the next byte of data (the content of the register specified in
the RAB). If AutoInc = 0, then another RESTART condition, followed by another DAB with R/W* = 0 and RAB, is
expected from the master device. The master device then issues another RESTART, followed by another DAB. After
SD
SC
1 - 8
RAB
9
ACK
Condition
Start
Condition
Stop
1 - 7
Device
8
R/W*
9
ACK
CH5101
acknowledge
CH5101
acknowledge
1 - 8
RAB
9
ACK
CH5101
acknowledge
1 - 8
Data
9
ACK
I
2
C
1 - 8
Data
9
ACK
CH5101
acknowledge
CH5101
acknowledge
SD
SC
1 - 8
9
RAB n
ACK
Start
Condition
Stop
Condition
CH5101
acknowledge
1 - 8
Data n
9
1 - 8
9
ACK
Data n+1
ACK
CH5101
acknowledge
CH5101
acknowledge
CH5101
acknowledge
1 - 7
Device ID
8
R/W*
9
ACK
I
2
C
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