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参数资料
| 型号： | CL10K30AQC240-1 |
| 英文描述： | FPGA |
| 中文描述： | FPGA的 |
| 文件页数： | 2/16页 |
| 文件大小： | 178K |
| 代理商： | CL10K30AQC240-1 |
LIBERATOR CL10K30A
Page 10
Symbol
Parameter
Min
Max
Min
Max
Min
Max Unit
tLUT
Look-up Table Delay for Data-in
0.8
1.1
1.5
ns
tCLUT
Look-up Table Delay for Carry-in
0.6
0.7
1.0
ns
tRLUT
Look-up Table Delay for LE Register
Feedback
1.2
1.5
2.0
ns
tPACKED Data-in to Packed Register Delay
0.6
1.0
ns
tEN
LE Register Enable Delay
1.3
1.5
2.0
ns
tCICO
Carry-in to Carry-out Delay
0.2
0.3
0.4
ns
tCGEN
Data-in to Carry-out Delay
0.8
1.0
1.3
ns
tCGENR
LE Register Feedback to Carry-out Delay
0.6
0.8
1.0
ns
tCASC
Cascade Chain Routing Ddelay
0.9
1.1
1.4
ns
tC
LE Register Control Signal Delay
1.1
1.3
1.7
ns
tCO
LE Register Clock-to-output Delay
0.4
0.6
0.7
ns
tCOMB
Combinatorial Delay
0.6
0.7
0.9
ns
tSU
LE Register Setup Time Before Clock
0.9
1.4
ns
tH
LE Register Hold Time After Clock
1.1
1.3
1.4
ns
tPRE
LE Register Preset Delay
0.5
0.6
0.8
ns
tCLR
LE Register Clear Delay
0.5
0.6
0.8
ns
tCH
Clock High Time
3.0
3.5
4.0
ns
tCL
Clock Low Time
3.0
3.5
4.0
ns
Speed: -1
Speed: -2
Speed: -3
10KA tbl 08C
AC Electrical Specifications cont.
Logic Element Timing Parameters[5]
Symbol
Parameter
Min
Max
Min
Max
Min
Max Unit
tDRR
Register to Register Delay via Four LEs,
Three Row Interconnects, and Four Local
Interconnects
11.0
13.0
17.0
ns
tINSU
Setup Time with Global Clock at IOE
Register
2.5
3.1
3.9
ns
tINH
Hold time with Global Clock at IOE Register
0.0
ns
tOUTCO
Output Data Hold Time After Clock
2.0
5.4
2.0
6.2
2.0
8.3
ns
Speed: -1
Speed: -2
Speed: -3
10KA tbl 07C
External Timing Parameters[4]
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相关代理商/技术参数 |
参数描述 |
|---|---|
| CL10K30AQC240-2 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:FPGA |
| CL10K30AQC240-3 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:FPGA |
| CL10K30AQI208-3 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:FPGA |
| CL10K30AQI240-3 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:FPGA |
| CL10K30ATC144-1 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:FPGA |
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