参数资料
型号: CM2030-A0TR
厂商: ON Semiconductor
文件页数: 7/11页
文件大小: 0K
描述: IC HDMI TX PORT P/I 38-TSSOP
标准包装: 1
系列: *
类型: *
应用: *
安装类型: 表面贴装
封装/外壳: 38-TFSOP (0.173",4.40mm 宽)裸露焊盘
供应商设备封装: 38-TSSOP
包装: 标准包装
其它名称: CM2030-A0TROSDKR
CM2030
http://onsemi.com
5
Figure 2. Dynamic DDC Pullups
(Discrete Top, CM2030 Bottom; 3.3 V ASIC Left, 5 V Cable Right)
I2C Low Level Shifting
In addition to the Dynamic Pullups described in the
previous section, the CM2030 also incorporates improved
I2C lowlevel shifting on the DDC_CLK_IN and
DDC_DAT_IN lines for enhanced compatibility.
Typical discrete NFET level shifters can advertise
specifications for low RDS[on], but usually state relatively
high V[GS] test parameters, requiring a ‘switch’ signal (gate
voltage) as high as 10 V or more. At a sink current of 4 mA
for the ASIC on DDC_XX_IN, the CM2030 guarantees no
more than 140 mV increase to DDC_XX_OUT, even with
a switching control of 2.5 V on LV_SUPPLY.
When I2C devices are driving the external cable, an
internal pulldown on DDC_XX_IN guarantees that the VOL
seen by the ASIC on DDC_XX_IN is equal to or lower than
DDC_XX_OUT.
Multiport DDC Multiplexing
By switching LV_SUPPLY, the DDC/HPD blocks can be
independently disabled by engaging their inherent
“backdrive” protection. This allows N:1 multiplexing of the
lowspeed HDMI signals without any additional FET
switches.
CONSUMER ELECTRONICS CONTROL (CEC)
The Consumer Electronics Control (CEC) line is a high
level command and control protocol, based on a single wire
multidrop open drain communication bus running at
approximately 1 kHz (See Figure 3). While the HDMI link
provides only a single pointtopoint connection, up to ten
(10) CEC devices may reside on the bus, and they may be
daisy chained out through other physical connectors
including other HDMI ports or other dedicated CEC links.
The high level protocol of CEC can be implemented in
a simple microcontroller or other interface with any I/OD
(input/opendrain) GPIO.
RX
TX
I/OD
GPIO
CEC
Figure 3. Typical mC I/OD Driver
To limit possible EMI and ringing in this potentially
complex connection topology, the rise and falltime of this
line are limited by the specification. However, meeting the
slewrate limiting requirements with additional discrete
circuitry in this bidirectional block is not trivial without an
additional RX/TX control line to limit the output slewrate
without affecting the input sensing (See Figure 4).
Figure 4. ThreePin External Buffer Control
RX
TX
TX_EN
CEC
Slew Rate
Limited
3State Buffer
Simple CMOS buffers cannot be used in this application
since the load can vary so much (total pullup of 27 kW to less
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