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参数资料
| 型号： | CME8000-DB |
| 厂商： | C-Max |
| 文件页数： | 6/22页 |
| 文件大小： | 0K |
| 描述： | BOARD DEMO FOR CME8000 |
| 标准包装： | 1 |
| 系列： | * |
| 模块/板类型： | 演示板 |
| 适用于相关产品： | CME8000 |
| 其它名称： | 561-1006 |
C-MAX Time Solutions
Data Sheet
CME8000
CLOCK, DT, PON, HLD
These pins are high impedant MOS-inputs and
require MOS-levels for operating
CLOCK
To run the IC it is necessary to apply the clock
chosen by CLKSEL.
All the timings given referred to this clock cycles.
In power down mode a clocking is not necessary.
HLD
AGC hold mode: HLD high (V HLD = V CC ) sets AGC
HLD off, HLD low (V HLD = 0) sets AGC HLD on,
that is it holds for a short time the AGC voltage.
This can be used to prevent the AGC from peak
BSI1, BSI2, DATA, DR
These 4 pin are MOS-outputs, which deliver
MOS-level.
ESD protection
VL
Pad 25
PIN 27
voltages, created by e.g. a stepper motor.
Additional, there will be internal hold function
generated, especially during read-out of data.
PON
PON must be either connected to V CC or GND.
If PON is connected to GND, the receiver will be
activated. The set-up time is typically 0.5 s after
BSI2
BSI1
PON
HLD
PIN 19
PIN 20
PIN 16
PIN 17
GNDL
Pad 16
PIN 18
PAD 17
PAD 18
PAD 14
PAD 15
Figure 11.
applying GND at this pin. If PON is connected to
V CC , the receiver will switch to power-down mode.
A power down period of min. 2msec is necessary
after switching on the power supply and before
switching to another protocol.
ESD protection
VL
Pad 25
PIN 27
CLOCK
DT
PON
HLD
PIN 24
PIN 21
PIN 16
PIN 17
GNDL
Pad 16
PIN 18
PAD 22
PAD 19
PAD 14
PAD 15
Figure 10.
SPEC No.
CME8000
Revision
B.15
State
09.03.07
C-MAX printed
03.05.2007
Version
English
Page
6 of 22
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