参数资料
型号: CMI8788
厂商: C-Media Electronics Inc.
英文描述: High Performance PCI Audio Processor
中文描述: 高性能的PCI音频处理器
文件页数: 6/29页
文件大小: 780K
代理商: CMI8788
C-Media High Performance PCI Audi o Controller
Oxygen
TMHD CMI8788 Datasheet v0.6
13
C-MEDIA CONFIDENTIAL
XAC97_BCLK
63
DI, PU AC97 serial clock input8
XAC97_SDI0
62
DI, PD AC97 serial data input 0
XAC97_SDI1/
XADC1_SDIN1
58
DI, PD AC97 serial data input 1. This pin is shared with XADC1_SDIN1,
and determined by XSPI_DOUT/XA1 input configuration at the
rising edge of XRST.
XAC97_SYNC
61
DO
AC97 frame synchronization.
XAC97_SDO0
64
DO
AC97 serial data output 0.
XAC97_SDO1
59
DO
AC97 serial data output 1.
XAC97_RST0
60
DO
AC97 codec reset 0.
XAC97_RST1
57
DO
AC97 codec reset 1.
XAC97_MCLK
65
DO
AC97 master clock 24.5760M for AC97 codec.
Serial Port Interface
XSPI_DIN/
XMSDA
73
DIO, PU SPI data input. This pin is shared with 2-wire master serial data.
XSPI_CLK/
XMSCL
74
DIO, PU SPI clock output. This pin is shared with 2-wire master serial
clock.
XSPI_DOUT/
XA1
75
DIO, PU SPI data output. This pin is shared with 2 -wire Codec address A1.
It is also used as XAC97_SDI1 and XADC1_SDIN1
configuration at the rising edge of XRST (input, 1: XAC97_SDI1,
0: XADC1_SDIN1).
XSPI_CEN0/
XA0
77
DIO, PU SPI chip enable, which select the codec #0 to be controlled. It is
shared with I2C Codec address A0. It is also used as XGPIO3~4
and SSCL/SSDA configuration (input, 1: GPIO3~4, 0:
SSCL/SSDA) at the rising edge of XRST.
XSPI_CEN1/
XCID0
78
DIO, PU SPI chip enable, which select the codec #1 to be controlled
(output). It is shared with codec ID 0 configuration (input) at the
rising edge of XRST.
XSPI_CEN2/
XCID1
79
DIO, PU SPI chip enable, which select the codec #2 to be controlled
(output). It is shared with codec ID 1 configuration (input) at the
rising edge of XRST.
XSPI_CEN3/
XCID2
80
DIO, PU SPI chip enable, which select the codec #3 to be controlled
(output). It is shared with codec ID 2 configuration (input) at the
rising edge of XRST.
XSPI_CEN4/
XEESK
68
DO
SPI chip enable, which select the codec #4 to be controlled. It is
shared with EEPROM serial clock.
XSPI_CEN5/
XEEDO
69
DO
SPI chip enable, which select the codec #5 to be controlled. It is
shared with EEPROM serial data out.
2-Wire Master Serial Bus
XMSDA/
XSPI_DIN
73
DIO, PU 2-wire serial bus data. This pin is shared with SPI data input.
XMSCL/
XSPI_CLK
74
DIO, PU 2-wire serial bus clock. This pin is shared with SPI clock output.
XA1/
XSPI_DOUT
75
DIO, PU 2-wire serial bus codec address A1. This pin is shared with SPI
data output. It is also used as XAC97_SDI1 and XADC1_SDIN1
configuration at the rising edge of XRST (input, 1: XAC97_SDI1,
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