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参数资料
| 型号： | CMK2-67025V-20 |
| 厂商： | ATMEL CORP |
| 元件分类： | SRAM |
| 英文描述： | 8K X 16 DUAL-PORT SRAM, 20 ns, PQFP84 |
| 封装： | 0.050 INCH, MQFP-84 |
| 文件页数： | 14/23页 |
| 文件大小： | 257K |
| 代理商： | CMK2-67025V-20 |
M 67025
MATRA MHS
Rev. D (29/09/95)
21
Waveform of Interrupt Timing (1)
Notes :
1. All timing is the same for left and right ports. Port “A” may bei either the left or right port. Port “B” is the port opposite from “A”.
2. See Interrupt truth table.
3. Timing depends on which enable signal is asserted last.
4. Timing depends on which enable signal is de-asserted first.
32-bit Master/Slave Dual-Port Memory Systems
Notes :
1. No arbitration in M 67025 (SLAVE). BUSY-IN inhibits write in M 67025 SLAVE.
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