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参数资料
| 型号： | CNW4506 |
| 英文描述： | Intelligent Power Module and Gate Drive Interface Optocouplers |
| 中文描述： | 智能功率模块和门极驱动接口光电耦合器 |
| 文件页数： | 14/14页 |
| 文件大小： | 267K |
| 代理商： | CNW4506 |
1-62
because the current through C
LEDO1
has the effect of trying to pull the
output high (toward a CMR failure)
at the same time the LED current is
being reduced. For this reason, the
recommended LED drive circuit
(Figure 19) places the current set-
ting resistor in series with the LED
cathode. Figure 24 is the AC equiv-
alent circuit for Figure 19 during
common mode transients. In this
case, the LED current is not
reduced during a +dVcm/dt tran-
sient because the current flowing
through the package capacitance is
supplied by the power supply.
During a -dVcm/dt transient, how-
ever, the LED current is reduced by
the amount of current flowing
through C
LEDN
. But, better CMR
performance is achieved since the
current flowing in C
LEDO1
during a
negative transient acts to keep the
output low.
Coupling to the LED and output
pins is also affected by the connec-
tion of pins 1 and 4. If CMR is
limited by perturbations in the LED
on current, as it is for the recom-
mended drive circuit (Figure 19),
pins 1 and 4 should be connected to
the input circuit common. However,
if CMR performance is limited by
direct coupling to the output when
the LED is off, pins 1 and 4 should
be left unconnected.
CMR with the LED Off
(CMR
H
)
A high CMR LED drive circuit must
keep the LED off (V
F
≤
V
F(OFF)
)
during common mode transients.
For example, during a +dVcm/dt
transient in Figure 24, the current
flowing through C
LEDN
is supplied
by the parallel combination of the
LED and series resistor. As long as
the voltage developed across the
resistor is less than V
F(OFF)
the LED
will remain off and no common
mode failure will occur. Even if the
LED momentarily turns on, the 100
pF capacitor from pins 6-5 will
keep the output from dipping below
the threshold. The recommended
LED drive circuit (Figure 19) pro-
vides about 10 V of margin between
the lowest optocoupler output
voltage and a 3 V IPM threshold
during a 15 kV/
μ
s transient with
V
CM
= 1500 V. Additional margin
can be obtained by adding a diode
in parallel with the resistor, as
shown by the dashed line connec-
tion in Figure 24, to clamp the
voltage across the LED below
V
F(OFF)
.
Since the open collector drive cir-
cuit, shown in Figure 25, cannot
keep the LED off during a +dVcm/
dt transient, it is not desirable for
applications requiring ultra high
CMR
H
performance. Figure 26 is
the AC equivalent circuit for Figure
25 during common mode
transients. Essentially all the
current flowing through C
LEDN
during a +dVcm/dt transient must
be supplied by the LED. CMR
H
failures can occur at dV/dt rates
where the current through the LED
and C
LEDN
exceeds the input
threshold. Figure 27 is an
alternative drive circuit which does
achieve ultra high CMR
performance by shunting the LED
in the off state.
IPM Dead Time and
Propagation Delay
Specifications
The HCPL-4506, HCPL-0466 and
HCNW4506 include a Propagation
Delay Difference specification
intended to help designers minimize
“dead time” in their power inverter
designs. Dead time is the time
period during which both the high
and low side power transistors (Q1
and Q2 in Figure 28) are off. Any
overlap in Q1 and Q2 conduction
will result in large currents flowing
through the power devices between
the high and low voltage motor rails.
To minimize dead time the designer
must consider the propagation
delay characteristics of the opto-
coupler as well as the characteris-
tics of the IPM IGBT gate drive
circuit. Considering only the delay
characteristics of the optocoupler
(the characteristics of the IPM
IGBT gate drive circuit can be
analyzed in the same way) it is
important to know the minimum
and maximum turn-on (t
PHL
) and
turn-off (t
PLH
) propagation delay
specifications, preferably over the
desired operating temperature
range.
The limiting case of zero dead time
occurs when the input to Q1 turns
off at the same time that the input
to Q2 turns on. This case
determines the minimum delay
between LED1 turn-off and LED2
turn-on, which is related to the
worst case optocoupler propagation
delay waveforms, as shown in
Figure 29. A minimum dead time of
zero is achieved in Figure 29 when
the signal to turn on LED2 is
delayed by (t
PLH max
- t
PHL min
) from
the LED1 turn off. Note that the
propagation delays used to calcu-
late PDD are taken at equal temper-
atures since the optocouplers under
consideration are typically mounted
in close proximity to each other.
(Specifically, t
PLH max
and t
PHL min
in the previous equation are not the
same as the t
PLH max
and t
PHL min
,
over the full operating temperature
range, specified in the data sheet.)
This delay is the maximum value for
the propagation delay difference
specification which is specified at
450 ns for the HCPL-4506, HCPL-
0466 and HCNW4506 over an
operating temperature range of
-40
°
C to 100
°
C.
Delaying the LED signal by the
maximum propagation delay dif-
ference ensures that the minimum
dead time is zero, but it does not
tell a designer what the maximum
dead time will be. The maximum
dead time occurs in the highly
unlikely case where one optocoup-
ler with the fastest t
PLH
and another
with the slowest t
PHL
are in the
same inverter leg. The maximum
dead time in this case becomes the
sum of the spread in the t
PLH
and
t
PHL
propagation delays as shown in
Figure 30. The maximum dead time
is also equivalent to the difference
between the maximum and mini-
mum propagation delay difference
specifications. The maximum dead
time (due to the optocouplers) for
the HCPL-4506, HCPL-0466 and
HCNW4506 is 600 ns (= 450ns -
(-150 ns)) over an operating
temperature range of -40
°
C to
100
°
C.
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