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| 型号： | COP8CBR9IMT8/NOPB |
| 厂商： | National Semiconductor |
| 文件页数： | 61/111页 |
| 文件大小： | 0K |
| 描述： | IC MCU EEPROM 8BIT 32K 48-TSSOP |
| 标准包装： | 38 |
| 系列： | COP8™ 8C |
| 核心处理器： | COP8 |
| 芯体尺寸： | 8-位 |
| 速度： | 20MHz |
| 连通性： | Microwire/Plus（SPI），UART/USART |
| 外围设备： | 欠压检测/复位，POR，PWM，WDT |
| 输入/输出数： | 39 |
| 程序存储器容量： | 32KB（32K x 8） |
| 程序存储器类型： | 闪存 |
| RAM 容量： | 1K x 8 |
| 电压 - 电源 (Vcc/Vdd)： | 2.7 V ~ 5.5 V |
| 数据转换器： | A/D 16x10b |
| 振荡器型： | 内部 |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 48-TFSOP（0.240"，6.10mm 宽） |
| 包装： | 管件 |
| 其它名称： | *COP8CBR9IMT8 *COP8CBR9IMT8/NOPB COP8CBR9IMT8 COP8CBR9IMT8-ND |
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SNOS535I – OCTOBER 2000 – REVISED MARCH 2013
NOTE
As with the HALT mode, it is necessary to program two NOP's to allow clock
resynchronization upon return from the IDLE mode. The NOP's are placed either at the
beginning of the IDLE Timer interrupt routine or immediately following the “enter IDLE mode”
instruction.
For more information on the IDLE Timer and its associated interrupt, see the description in the Timers
section.
5.12.4 DUAL CLOCK MODE OPERATION
This mode of operation allows for high speed operation of the Core clock and low speed operation of the
Idle Timer. This mode can be entered from either the High Speed mode or the Low Speed mode.
To enter from the High Speed mode, the following sequence must be followed:
1. Software sets the LSON bit to 1.
2. Software waits until the low speed oscillator has stabilized. See Table 5-2.
3. Software sets the DCEN bit to 1.
To enter from the Low Speed mode, the following sequence must be followed:
1. Software sets the HSON bit to 1.
2. Software waits until the high speed oscillator has stabilized. See Table 5-2, Startup Times.
3. Software clears the CCKSEL bit to 0.
5.12.4.1 Dual Clock HALT Mode
The fully static architecture of this device allows the state of the microcontroller to be frozen. This is
accomplished by stopping the high speed clock of the device during the HALT mode. The processor can
be forced to exit the HALT mode and resume normal operation at any time. The low speed clock remains
on during HALT in the Dual Clock mode.
During normal operation, the actual power consumption depends heavily on the clock speed and operating
voltage used in an application and is shown in the Electrical Specifications. In the HALT mode, the device
only draws a small leakage current, plus current for the BOR feature (if enabled), plus the 32 kHz
oscillator current, plus any current necessary for driving the outputs. Since total power consumption is
affected by the amount of current required to drive the outputs, all I/Os should be configured to draw
minimal current prior to entering the HALT mode, if possible.
5.12.4.1.1 Entering The Dual Clock Halt Mode
The device enters the HALT mode under software control when the Port G data register bit 7 is set to 1.
All processor action stops in the middle of the next instruction cycle, and power consumption is reduced to
a very low level. In order to expedite exit from HALT, the low speed oscillator is left running when the
device is Halted in the Dual Clock mode. However, the Idle Timer will not be clocked.
5.12.4.1.2 Exiting The Dual Clock Halt Mode
When the HALT mode is entered by setting bit 7 of the Port G data register, there is a choice of methods
for exiting the HALT mode: a chip Reset using the RESET pin or a Multi-Input Wake-up. The Reset
method and Multi-Input Wake-up method can be used with any clock option.
5.12.4.1.3 HALT Exit Using Reset
A device Reset, which is invoked by a low-level signal on the RESET input pin, takes the device out of the
Dual Clock mode and puts it into the High Speed mode.
Copyright 2000–2013, Texas Instruments Incorporated
Functional Description
53
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