参数资料
型号: COP8SGA544Q9
厂商: National Semiconductor Corporation
元件分类: DC/DC变换器
英文描述: RxxPxx Series - Econoline Unregulated DC-DC Converters; Input Voltage (Vdc): 12V; Output Voltage (Vdc): 15V; Power: 1W; EN 60950 certified, rated for 250VAC; UL-60950-1 / CSA C22.2 certified; 5.2kVDC Isolation for 1 Minute; Optional Continuous Short Circuit Protected; 2 Chamber Transformer System; UL94V-0 Package Material; Efficiency to 80%
中文描述: 8位的CMOS基于ROM和OTP微控制器具有8K到32K的内存,2个比较器和USART
文件页数: 8/62页
文件大小: 913K
代理商: COP8SGA544Q9
DC Electrical Characteristics
(Continued)
40C
T
A
+85C unless otherwise specified.
Parameter
Output Current Levels
D Outputs
Source
Conditions
Min
Typ
Max
Units
V
CC
= 4.5V, V
OH
= 3.3V
V
CC
= 2.7V, V
OH
= 1.8V
V
CC
= 4.5V, V
OL
= 1.0V
V
CC
= 2.7V, V
OL
= 0.4V
0.4
-0.2
10
2
mA
mA
mA
mA
Sink
All Others
Source (Weak Pull-Up Mode)
V
CC
= 4.5V, V
OH
= 2.7V
V
CC
= 2.7V, V
OH
= 1.8V
V
CC
= 4.5V, V
OH
= 3.3V
V
CC
= 2.7V, V
OH
= 1.8V
V
CC
= 4.5V, V
OL
= 0.4V
V
CC
= 2.7V, V
OL
= 0.4V
V
CC
= 5.5V
10.0
-2.5
0.4
-0.2
1.6
0.7
2
110
-33
μA
μA
mA
mA
mA
mA
μA
Source (Push-Pull Mode)
Sink (Push-Pull Mode)
TRI-STATE Leakage
Allowable Sink Current per Pin (Note 9)
D Outputs and L0 to L3
All Others
Maximum Input Current without Latchup
(Note 7)
RAM Retention Voltage, Vr
V
CC
Rise Time from a V
CC
2.0V
EPROM Data Retenton (Note 8), (Note 9)
Input Capacitance
Load Capacitance on D2
+2
15
3
mA
mA
Room Temp.
±
200
mA
2.0
12
V
μs
(Note 10)
T
A
= 55C
(Note 9)
(Note 9)
>
29
years
pF
pF
7
1000
AC Electrical Characteristics
40C
T
A
+85C unless otherwise specified.
Parameter
Instruction Cycle Time (t
C
)
Crystal/Resonator, External
Conditions
Min
Typ
Max
Units
4.5V
V
CC
5.5V
2.7V
V
CC
4.5V
4.5V
V
CC
5.5V
4.5V
V
CC
5.5V
fr = Max
fr = 10 MHz Ext Clock
fr = 10 MHz Ext Clock
0.67
2
μs
μs
μs
%
%
ns
ns
ns
R/C Oscillator (Internal)
Frequency Variation (Note 9)
External CKI Clock Duty Cycle (Note 9)
Rise Time (Note 9)
Fall Time (Note 9)
MICROWIRE Setup Time (t
UWS
) (Note
11)
MICROWIRE Hold Time (t
UWH
) (Note
11)
MICROWIRE Output Propagation Delay
(t
UPD
) (Note 11)
Input Pulse Width (Note 9)
Interrupt Input High Time
Interrupt Input Low Time
Timer 1, 2, 3, Input High Time
Timer 1 2, 3, Input Low Time
Reset Pulse Width
2
±
35
45
55
8
5
20
56
ns
220
ns
1
1
1
1
1
t
C
t
C
t
C
t
C
μs
Note 3:
t
C
= Instruction cycle time.
C
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