参数资料
型号: COP8SGE728N8XXX
厂商: NATIONAL SEMICONDUCTOR CORP
元件分类: 微控制器/微处理器
英文描述: 8-BIT, OTPROM, 15 MHz, MICROCONTROLLER, PDIP28
封装: PLASTIC, DIP-28
文件页数: 6/62页
文件大小: 840K
代理商: COP8SGE728N8XXX
4.0 Pin Descriptions (Continued)
Note: For compatibility with existing software written for COP888xG devices
and with existing Mask ROM devices, a read of the Port I input pins
(address xxD7) will return the same data as reading the Port F input
pins (address xx96). It is recommended new applications which will go
to production with the COP8SGx use the Port F addresses. Note that
compatible ROM devices contains the input only Port I instead of the
bi-directional Port F.
Port D is an 8-bit output port that is preset high when RESET
goes low. The user can tie two or more D port outputs
(except D2) together in order to get a higher drive.
Note: Care must be exercised with the D2 pin operation. At RESET, the
external loads on this pin must ensure that the output voltages stay
above 0.7 VCC to prevent the chip from entering special modes. Also
keep the external loading on D2 to less than 1000 pF.
5.0 Functional Description
The architecture of the devices are a modified Harvard ar-
chitecture. With the Harvard architecture, the program
memory ROM is separated from the data store memory
(RAM). Both ROM and RAM have their own separate ad-
dressing space with separate address buses. The architec-
ture, though based on the Harvard architecture, permits
transfer of data from ROM to RAM.
5.1 CPU REGISTERS
The CPU can do an 8-bit addition, subtraction, logical or shift
operation in one instruction (t
C) cycle time.
There are six CPU registers:
A is the 8-bit Accumulator Register
PC is the 15-bit Program Counter Register
PU is the upper 7 bits of the program counter (PC)
PL is the lower 8 bits of the program counter (PC)
B is an 8-bit RAM address pointer, which can be optionally
post auto incremented or decremented.
X is an 8-bit alternate RAM address pointer, which can be
optionally post auto incremented or decremented.
S is the 8-bit Segment Address Register used to extend the
lower half of the address range (00 to 7F) into 256 data
segments of 128 bytes each.
SP is the 8-bit stack pointer, which points to the subroutine/
interrupt stack (in RAM). With reset the SP is initialized to
RAM address 02F Hex (devices with 64 bytes of RAM), or
initialized to RAM address 06F Hex (devices with 128 bytes
of RAM).
All the CPU registers are memory mapped with the excep-
tion of the Accumulator (A) and the Program Counter (PC).
5.2 PROGRAM MEMORY
The program memory consists of varies sizes of ROM.
These bytes may hold program instructions or constant data
(data tables for the LAID instruction, jump vectors for the JID
instruction, and interrupt vectors for the VIS instruction). The
program memory is addressed by the 15-bit program
counter (PC). All interrupts in the device vector to program
memory location 0FF Hex. The contents of the program
memory read 00 Hex in the erased state. Program execution
starts at location 0 after RESET.
DS101317-10
FIGURE 5. I/O Port Configurations
DS101317-12
FIGURE 6. I/O Port Configurations — Output Mode
DS101317-11
FIGURE 7. I/O Port Configurations — Input Mode
COP8SG
Family
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相关PDF资料
PDF描述
COP8SGR728M8XXX 8-BIT, OTPROM, 15 MHz, MICROCONTROLLER, PDSO28
COP8SGR744J3XXX 8-BIT, UVPROM, MICROCONTROLLER, CQCC44
COP8SGE744V8XXX 8-BIT, OTPROM, 15 MHz, MICROCONTROLLER, PQCC44
COP8SGE744V7XXX 8-BIT, OTPROM, 10 MHz, MICROCONTROLLER, PQCC44
COP8SGR740N7XXX 8-BIT, OTPROM, 10 MHz, MICROCONTROLLER, PDIP40
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