参数资料
| 型号： | COREU1PHY-AR |
| 厂商： | Microsemi SoC |
| 文件页数： | 3/8页 |
| 文件大小： | 0K |
| 描述： | IP MODULE COREU1PHY |
| 标准包装： | 1 |
| 系列： | * |
CoreU1PHY – UTOPIA Level 1 PHY Interface
Alternatively, the link-layer device may choose to stall in-
The CoreU1PHY will then
assert u1_rx_soc high,
between cells without deselecting the physical interface,
u1_tx_clk
u1_tx_clav
u1_tx_en
u1_tx_soc
indicating that the first word of the cell transfer is active
on the bus. Once a transfer has begun, all 53 or 54 bytes
of the cell are transferred without interruption.
If polling during the current transfer indicates that there
are no more cells available, or if the link-layer is unable
to receive another cell from the CoreU1PHY, the link-
layer may deselect the physical interface by de-asserting
u1_rx_en after receiving the last byte of the current cell,
u1_tx_data
P51 P52 P53 P54
XX
H1
H2
u1_rx_clk
Figure 4 ? TX Stalled by u1_tx_clav
If the link-layer has another cell to send to the physical
interface and if polling during the current cell indicates
that the CoreU1PHY is able to accept another cell, the
u1_rx_clav
u1_rx_en
u1_rx_soc
link-layer may send cells back-to-back, as illustrated in
u1_rx_data
P51
P52
P53
P54
XX
Figure 7 ? RX End of Transfer
u1_tx_clk
u1_tx_clav
u1_tx_en
u1_tx_soc
If the link-layer continues to enable the CoreU1PHY
during the last two bytes of the current cell transfer, and
one or more complete ATM cells are ready to be
transferred (u1_rx_avail is high), the CoreU1PHY will
send back-to-back cells, as shown in Figure 8 . If the user
interface indicates r_avail low (no data to send), but the
u1_tx_data
P51 P52 P53 P54 H1 H2 H3 H4 H5 H6
link-layer continues to assert
U1_rx_en low, the
Figure 5 ? TX Back-to-Back Transfer
CoreU1PHY interface will remain idle until r_avail is
asserted high on the user interface and another cell
transfer begins.
RX Interface (Egress)
The RX interface operates in a similar manner. The
process begins with u1_rx_clav. If the user interface
indicates there is at least one complete cell available for
transfer by asserting r_avail high, the core responds with
u1_rx_clav high; otherwise, u1_rx_clav is asserted low
and the link-layer device must wait until the user logic
u1_rx_clk
u1_rx_clav
u1_rx_en
u1_rx_soc
indicates that a cell is available for transfer.
To begin receiving cells on the RX interface, the link-
u1_rx_data
P51 P52 P53 P54 H1 H2 H3 H4 H5
layer must select the CoreU1PHY by asserting u1_rx_en
low ( Figure 6 ).
u1_rx_clk
u1_rx_clav
u1_rx_en
u1_rx_soc
Figure 8 ? RX Back-to-Back Transfer
u1_rx_data
Figure 6 ? RX Start of Cell Transfer
H1 H2
v4.0
3
相关PDF资料 |
PDF描述 |
|---|---|
| CORR-8BIT-XM-UT2 | SITE LICENSE IP CORRELATOR XP |
| CP2-GSA-L | CONN SHIELD LOWER TYPE A 22 |
| CP2-HSA110-1 | CONN SHROUD CPCI 2MM TYPE A 22 |
| CP2-HSC055-4 | CONN SHROUD CPCI 2MM TYPE C 11 |
| CP2-K3567-SR-F | COMPACT PCI - MISC |
相关代理商/技术参数 |
参数描述 |
|---|---|
| COREU1PHY-EV | 制造商:ACTEL 制造商全称:Actel Corporation 功能描述:CoreU1PHY - UTOPIA Level 1 PHY Interface |
| COREU1PHY-SN | 制造商:ACTEL 制造商全称:Actel Corporation 功能描述:CoreU1PHY - UTOPIA Level 1 PHY Interface |
| COREU1PHY-SR | 制造商:ACTEL 制造商全称:Actel Corporation 功能描述:CoreU1PHY - UTOPIA Level 1 PHY Interface |
| COREU1PHY-UR | 制造商:ACTEL 制造商全称:Actel Corporation 功能描述:CoreU1PHY - UTOPIA Level 1 PHY Interface |
| COREU1PHY-XX | 制造商:ACTEL 制造商全称:Actel Corporation 功能描述:CoreU1PHY - UTOPIA Level 1 PHY Interface |
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