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参数资料
| 型号： | CORR-8BIT-P2-UT2 |
| 厂商： | Lattice Semiconductor Corporation |
| 文件页数： | 3/10页 |
| 文件大小： | 0K |
| 描述： | SITE LICENSE IP CORRELATOR ECP2 |
| 标准包装： | 1 |
| 系列： | * |
| 其它名称： | CORR8BITP2UT2 |
Lattice Semiconductor
Correlator IP Core
Since the coef?cients in a complex correlation are restricted to the values {+1,-1}, the multiplications in Equation 3
simplify to inversions of the d re and d im terms, and the whole equation reduces to a series of additions and subtrac-
tions. The Correlator IP core performs these inversions and sums the results to produce a new result value r for
each new d re and d im term input to the core. In this case, the result sequence will have two terms, a real term and
an imaginary term.
Functional Description
The Correlator IP core is composed of the following functional blocks:
? State Machine – Controls the ?ow of data received from the user. Generates the starting pointer values neces-
sary to read/write the Tap Memory and stores the pointer values in the Channel Memory. Stores the starting
pointer values for the next correlation operation in the input FIFO. Generates the “shiftby” value for the aligner.
? Channel Memory – Stores the pointer to the location in Tap Memory to write the next data value.
? Input FIFO – Stores the pointer to the starting point in Tap and Coef?cient Memories for the next correlation.
? Tap Memory – Stores the data terms (d i ).
? Coef?cient Memory – Stores the coef?cient terms (c i ).
? Aligner – Aligns data and coef?cients read from memory for the correlation operation.
? Correlator – Performs the equivalent of the multiplication operations in Equations 1 and 2.
? Adder/Accumulator – Performs the addition and subtraction operations in Equations 1 and 2.
Correlator Input and Output Data
The Correlator IP core accepts a new input data value for a channel and writes that value into Tap Memory. When it
is ready to perform the next correlation operation for that channel, the new data value will be included in the corre-
lation, along with enough “old” data already in memory to completely ?ll the correlation window. The Tap Memory is
a circular buffer which contains a correlation window’s worth of data. As each new value is added to Tap Memory
for a particular channel, a correlation operation needs to be run and completed before the next new value is added
to memory for that channel. New data can be written into Tap Memory for channels other than the one the Correla-
tor is operating on, however it is the user’s responsibility to insure that a correlation operation is done for a particu-
lar channel before new data is written into memory for that same channel. This is easy to do for a large number of
channels where new data is written to channels in a round-robin sequence, or if the Correlator throughput is not
stressed to its limit (i.e. unused cycles appear between correlations), but the problem can be dif?cult to manage for
small numbers of channels. The Correlator IP core will automatically prevent new data being written into Tap Mem-
ory and corrupting a correlation as long as the input FIFO depth (parameter 9) is set to 1.
Figures 2 and 3 show the timing of the user interface. The state machine accepts one new data value from the user
interface at a time. When the state machine is ready to accept a new input data word from the user interface it
asserts the crdy signal. The user interface then inputs din , chan_in , code_sel_in , block_start_in , and
asserts the irdy signal. When the state machine sees irdy go active, it will take the new data value from the user
interface. If the design has been con?gured for multiple channels, the state machine reads the pointer for that chan-
nel from the Channel Memory. This pointer value tells the state machine where in Tap Memory to write the data
value just received from the user interface. This pointer value will also be the starting point for the next correlation
operation, so this pointer value is stored in the Input FIFO until the next correlation operation is ready to start. Once
the present correlation operation ?nishes, or if no correlation operation was in progress when a new data value was
received, then the Input FIFO is read to determine the starting pointer for the next correlation. The state machine
begins reading the Tap and Coef?cient Memories at the starting pointer location, and it reads until it has read an
entire correlation window’s worth of data and coef?cients.
Figure 2 shows at time 173.5μs that crdy went active. The user provided a value of 0x3 for channel 0, and set the
code_sel_in to 1 which indicates which coef?cient sequence is to be used for the correlation of channel 0 data.
3
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相关代理商/技术参数 |
参数描述 |
|---|---|
| CORR-8BIT-PM-U2 | 功能描述:开发软件 Correlator IP Core User Config RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| CORR-8BIT-PM-UT2 | 功能描述:开发软件 8 BIT CORRELATOR IP RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| CORR-8BIT-SC-U2 | 功能描述:开发软件 Correlator IP Core User Config RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| CORR-8BIT-SC-UT2 | 功能描述:开发软件 8 BIT CORRELATOR IP RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| CORR-8BIT-X2-U2 | 功能描述:开发软件 Correlator IP Core User Config RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
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