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| 型号： | CPC5002G |
| 厂商： | IXYS Integrated Circuits Division |
| 文件页数： | 5/14页 |
| 文件大小： | 0K |
| 描述： | ISOLAT DGTL 3.75KVRMS 2CH 8-DIP |
| 标准包装： | 100 |
| 输入 - 1 侧/2 侧： | 2/0 |
| 通道数： | 2 |
| 电源电压： | 2.7 V ~ 5.5 V |
| 电压 - 隔离： | 3750Vrms |
| 数据速率： | 10Mbps |
| 传输延迟： | 81ns |
| 输出类型： | 开路漏极 |
| 封装/外壳： | 8-DIP（0.300"，7.62mm） |
| 供应商设备封装： | 8-DIP |
| 包装： | 管件 |
| 工作温度： | -40°C ~ 85°C |
| 其它名称： | CLA383 |
I NTEGRATED C IRCUITS D IVISION
1.9 Switching Specifications
CPC5002
Parameter
Conditions
Symbol
Min
Typ
Max
Units
Timing Specifications
Clock Frequency
Propagation Delay
Output Falling 1, 3
I SINK =6mA, C L =20pF
I F =1.5mA, V DD =3.3V,
R PU =499 ? , C L =20pF,
f MAX
t PHL
-
35
10
81
-
120
MHz
ns
Output Rising
2, 3
0.5V IN to 0.5V DD_OUT
t PLH
35
81
120
Pulse Width Distortion: |t PLH - t PLH |
As per t PHL and t PLH
PWD
85
ns
Propagation Delay Skew 3
Output Fall Time, 90% to 10%
As per t PHL and t PLH
I F =1.5mA, V DD =3.3V,
R PU =499 ? , C L =20pF
t PSK
t f
-
10
-
15
50
-
ns
ns
Common Mode Specifications
Common Mode Transient Immunity
V CM =20V P-P , V DD =3.3V, T A =25°C
V OUT = High
V OUT = Low
V OUT >2V
V OUT <0.8V
CM H
CM L
5
7
-
-
-
-
kV/ ? s
1
2
3
Falling propagation delay can be reduced by increasing instantaneous LED current drive, typically by increasing C FWD .
Rising propagation delay depends on R PU , C L , and I F .
Increasing I F above 2 ? I TH (by reducing R S ) increases the rising propagation delay.
Propagation Delay Skew is the worst case difference propagation delay, High to Low and Low to High between the two channels of a CPC5002
when measured using the test circuit shown below, which is tuned for approximately even rising and falling delays.
1.10 Propagation Delay Test Circuit
27pF
? CPC5002
V DD
3.3 V
2k Ω
I F
V OUT
R PU
499 Ω
C L
20pF
R03
www.ixysic.com
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