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参数资料
| 型号： | CPC7220WTR |
| 厂商： | CLARE INC |
| 元件分类： | 多路复用及模拟开关 |
| 中文描述： | 1-CHANNEL, SGL POLE SGL THROW SWITCH, PQCC28 |
| 封装： | ROHS COMPLIANT, PLASTIC, LCC-28 |
| 文件页数： | 10/11页 |
| 文件大小： | 213K |
| 代理商： | CPC7220WTR |
www.clare.com
8
CPC7220
R00H
PRELIMINAR
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CPC7220 Description
The CPC7220 takes a serial stream of input data
along with a synchronous clock signal. As the clock
transits from low to high, the data at the input of
each shift register is shifted through from SR(n) to
SR(n+1). A high data bit, a "1," represents an ON
switch; a low data bit, a "0," represents an OFF
switch. Data is input and shifted through the internal
shift register until all eight shift register positions,
SR0 through SR7, are in the desired state.
D
IN: The data-in line presents data bits to the
CPC7220 to be shifted through the internal shift
register.
CLK: The clock signal's rising edge is associated
only with shifting data into and through the shift
register.
CL: The clear line overrides all other inputs. When
CL is high, the shift register is cleared to all 0s
and all latches are set low, which causes all output
switches to be turned OFF immediately. When CL is
low, all output switches remain in whatever state they
are in, ON or OFF, in response to CLK, latch inputs,
and the LE signal.
LE: latch enable controls the state of the latches
and thus the state of the eight switches. If LE is high,
then the latches do not change states, but retain their
most recent status: either ON or OFF. With LE high,
input data and CLK have no effect on the state of the
output switches. If LE is low, then all latch outputs
and their switch states follow the inputs from the shift
register. LE is overridden by CL: no matter what state
LE is in, CL clears the latches. See table on page 10.
D
OUT: The data-out pin is the output of SR7. After
eight clock pulses, the first bit of eight input data bits
is shifted to SR7 and appears on D
OUT.
SW0 - SW7: The CPC7220 provides eight high-
voltage SPST output switches with a typical on-
resistance of 20
Ω. The two connections of each
switch are not polarity-sensitive.
V
PP and VNN: Voltage inputs to the level shifters for
each switch channel that translate the voltage level
of the latch output signals to an appropriate level for
the voltages being switched.
The high-voltage output switches are turned on and
off in response to the data sent into the latches from
the shift register: data 0 turns a switch OFF, data 1
turns a switch ON.
Two or more CPC7220 devices can be cascaded to
form an n-switch arrangement. The D
OUT pin of the
first is connected to the D
IN pin of the next in the
series. All devices are connected to the same clock
(CLK) signal. LE of all devices would normally be
connected, as would CL, but this is not necessary.
The first data bit applied to D
IN of the CPC7220,
whether it's a single device or several cascaded
devices, ripples through to the last switch output in
line after the application of a full clocking sequence
of 8 clock pulses per CPC7220. Setting the serial I/O
device to output the most significant bit (MSB) first,
results in the MSB appearing on SW7 of the last
device in line after a full clocking sequence.
CL
DIN
CLK
LE
SW0
SW7
SW0
SW7
SW0
SW7
DOUT
LE
CL
DIN
CLK
DOUT
LE
CL
DIN
CLK
DOUT
LE
CL
DIN
CLK
CPC7220
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| CPC7232W | 功能描述:模拟开关 IC 8-Channel High Voltage Analog Switch w/ Bleeder Resisitors 28-lead PLCC in tubes RoHS:否 制造商:Texas Instruments 开关数量:2 开关配置:SPDT 开启电阻（最大值）:0.1 Ohms 切换电压（最大）: 开启时间（最大值）: 关闭时间（最大值）: 工作电源电压:2.7 V to 4.5 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:DSBGA-16 |
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