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| 型号： | CPC7581BC |
| 厂商： | CLARE INC |
| 元件分类： | 通信及网络 |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, PDSO16 |
| 封装： | ROHS COMPLIANT, SOIC-16 |
| 文件页数： | 3/17页 |
| 文件大小： | 526K |
| 代理商： | CPC7581BC |
CPC7581
R05
www.clare.com
11
2.2.1 Make-Before-Break Operation Logic Table (Ringing to Talk Transition)
To use break-before-make ringing switch release
timing, assert TSD during ringing. This causes the
operational sequence shown in “Break-Before-Make
page 11 to occur.
2.2.2 Break-Before-Make Operation Logic Table (Ringing to Talk Transition)
Logic states and explanations are given in “Truth Table”
2.3 Data Latch
The CPC7581 has an integrated data latch. The latch
operation is controlled by logic-level input pin 11
(LATCH). The data input of the latch is pin 10
(INRINGING), while the output of the data latch is an
internal node used for state control. When the LATCH
control pin is at logic 0, the data latch is transparent
and data control signals flow directly through to state
control. A change in input will be reflected in a change
is switch state. When the LATCH control pin is at logic
1, the data latch is active and a change in input control
will not affect switch state. The switches will remain in
the position they were in when the LATCH changed
from logic 0 to logic 1 and will not respond to changes
in input as long as the latch is at logic 1. The TSD input
is not tied to the data latch. Therefore, TSD is not
affected by the LATCH input and the TSD input will
override state control.
2.4 TSD
The thermal shutdown mechanism activates when the
device die temperature reaches a minimum of 110° C,
placing the device in the all-off state regardless of
logic input. During thermal shutdown mode, pin 8
(TSD) will read a nominal 0 V. Normal output of TSD is
typically equal to VDD.
If presented with a short duration transient such as a
lightning event, the thermal shutdown feature will
typically not activate. But in an extended power-cross
event, the device temperature will rise and the thermal
shutdown will activate forcing the switches to the all-off
state. At this point the current measured through the
break switches (SW1 and SW2) will drop to zero.
Once the device enters thermal shutdown it will
remain in the all-off state until the temperature of the
device drops below the de-activation level of the
thermal shutdown circuit. This permits the device to
State
INRINGING
Latch
TSD
Timing
Break
Switches
Ringing
Return
Switch
(SW3)
Ringing
Switch
(SW4)
Ringing
1
0Z
-Off
On
Make-
Before-
Break
0
SW4 waiting for next zero-current crossing to
turn off. Maximum time is one-half of the ringing
cycle. In this transition state, current that is
limited to the dc break switch current limit value
will be sourced from the ring node of the SLIC.
On
Off
On
Talk
0
Zero-cross current has occurred
On
Off
State
INRINGING
Latch
TSD
Timing
Break
Switches
Ringing
Return
Switch
(SW3)
Ringing
Switch
(SW4)
Ringing
1
0
Z-
Off
On
All-off
1
0
Hold this state for one-half of the ringing cycle.
SW4 waiting for zero current to turn off.
Off
On
All-off
1
Zero current has occurred. SW4 has opened
Off
Talk
0
Z
Release break switches
On
Off
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