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参数资料
| 型号： | CPC7582BC |
| 厂商： | CLARE INC |
| 元件分类： | 通信及网络 |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, PDSO16 |
| 封装： | ROHS COMPLIANT, SOIC-16 |
| 文件页数： | 6/19页 |
| 文件大小： | 566K |
| 代理商： | CPC7582BC |
CPC7582
14
www.clare.com
R05
the CPC7582 switches when pulled to a logic low.
Although logically disabled, if the ringing switch (SW4)
is active (closed), it will remain closed until the next
current zero crossing event.
As shown in the table “Break-Before-Make Operation
this operation is similar to the one shown in
page 13, except in the method used to select the all off
state, and in when the INRINGING and INTEST inputs
are reconfigured for the talk state.
1.
Pull TSD to a logic low to end the ringing state.
This opens the ringing return switch (SW3) and
prevents any other switches from closing.
2.
Keep TSD low for at least one-half the duration of
the ringing cycle period to allow sufficient time for
a zero crossing current event to occur and for the
circuit to enter the break before make state.
3.
During the TSD low period, set the INRINGING and
INTEST inputs to the talk state (0, 0).
4.
Release TSD, allowing the internal pull-up to
activate the break switches.
When using TSD as an input, the two recommended
states are 0 (overrides logic input pins and forces an
all off state) and float (allows switch control via logic
input pins and the thermal shutdown mechanism is
active). This requires the use of an open-collector type
buffer.
Forcing TSD to a logic high disables the thermal
shutdown circuit and is therefore not recommended as
this could lead to device damage or destruction in the
presence of excessive tip or ring potentials.
2.2.6 Break-Before-Make Operation for all Version (Ringing to Talk Transition)
2.3 Data Latch
The CPC7582 has an integrated data latch. The latch
operation is controlled by logic-level input pin 11
(LATCH). The data input of the latch is pin 10
(INRINGING) and pin 9 (INTEST) of the device while the
output of the data latch is an internal node used for
state control. When LATCH control pin is at logic 0, the
data latch is transparent and data control signals flow
directly through to state control. A change in input will
be reflected in the switch state. When LATCH control
pin is at logic 1, the data latch is active and a change
in input control will not affect switch state. The
switches will remain in the position they were in when
the LATCH changed from logic 0 to logic 1 and will not
respond to changes in input as long as the latch is at
logic 1. The TSD input is not tied to the data latch.
Therefore, TSD is not affected by the LATCH input and
the TSD input will override state control.
2.4 Thermal Shutdown
Setting TSD to +5 V allows switch control using the
logic inputs. This setting, however, also disables the
thermal shutdown circuit and is therefore not
recommended. When using logic controls via the input
pins, pin 7 (TSD) should be allowed to float. As a
result, the two recommended states when using pin 7
(TSD) as a control are 0, which forces the device to the
all-off state, or float, which allows logic inputs to
remain active. This requires the use of an
open-collector type buffer.
2.5 Ringing Switch Zero-Cross Current Turn Off
After the application of a logic input to turn SW4 off,
the ringing switch is designed to delay the change in
state until the next zero-crossing. Once on, the switch
requires a zero-current cross to turn off, and therefore
should not be used to switch a pure DC signal. The
State
INRINGING
INTEST LATCH
TSD
Timing
Break
Switches
Ringing
Return
Switch
(SW3)
Ringing
Switch
(SW4)
Test
Switches
Ringing
1
0
Floating
-
Off
On
Off
All-Off
0
Hold this state for at least one-half of the
ringing cycle. SW4 waiting for zero
current to turn off.
Off
On
Off
Break-
Before-
Make
0
SW4 has opened
Off
Talk
0
Floating
Close Break Switches
On
Off
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