参数资料
型号: CRD5381
厂商: Cirrus Logic Inc
文件页数: 15/16页
文件大小: 0K
描述: REFERENCE DESIGN CS5381 AUD ADC
标准包装: 1
ADC 的数量: 2
位数: 24
采样率(每秒): 192k
数据接口: 串行
输入范围: 6.1 Vpp
在以下条件下的电源(标准): 360mW @ 5V
工作温度: -10°C ~ 70°C
已用 IC / 零件: CS5381
已供物品: 板,CD
产品目录页面: 756 (CN2011-ZH PDF)
相关产品: CS5381-KZZR-ND - IC ADC AUD 120DB 192KHZ 24-TSSOP
CS5381-KSZR-ND - IC ADC AUD 120DB 192KHZ 24-SOIC
598-1092-5-ND - IC ADC AUD 120DB 192KHZ 24-TSSOP
598-1091-5-ND - IC ADC AUD 120DB 192KHZ 24-SOIC
其它名称: 598-1592
IDT / ICS 3.3V, 2.5V LVPECL CLOCK GENERATOR
8
ICS843031AG-01 REV. A NOVEMBER 11, 2008
ICS843031-01
FEMTOCLOCKS CRYSTAL-TO-3.3V, 2.5V LVPECL CLOCK GENERATOR
LVCMOS TO XTAL INTERFACE
The XTAL_IN input can accept a single-ended LVCMOS signal
through an AC coupling capacitor. A general interface diagram is
shown in
Figure 3. The XTAL_OUT pin can be left floating. The
input edge rate can be as slow as 10ns. For LVCMOS inputs, it is
recommended that the amplitude be reduced from full swing to
half swing in order to prevent signal interference with the power
rail and to reduce noise. This configuration requires that the output
FIGURE 3. GENERAL DIAGRAM FOR LVCMOS DRIVER TO XTAL INPUT INTERFACE
impedance of the driver (Ro) plus the series resistance (Rs) equals
the transmission line impedance. In addition, matched termination
at the crystal input will attenuate the signal in half. This can be
done in one of two ways. First, R1 and R2 in parallel should equal
the transmission line impedance. For most 50
Ω applications, R1
and R2 can be 100
Ω. This can also be accomplished by removing
R1 and making R2 50
Ω.
R2
Zo = 50
VDD
Ro
Zo = Ro + Rs
R1
VDD
XTAL_IN
XTAL_OUT
.1uf
Rs
TERMINATION FOR 3.3V LVPECL OUTPUTS
The clock layout topology shown below is a typical termination
for LVPECL outputs. The two different layouts mentioned are
recommended only as guidelines.
FOUT and nFOUT are low impedance follower outputs that gen-
erate ECL/LVPECL compatible outputs. Therefore, terminating
resistors (DC current path to ground) or current sources must be
used for functionality. These outputs are designed to drive 50
Ω
FIGURE 4B. LVPECL OUTPUT TERMINATION
FIGURE 4A. LVPECL OUTPUT TERMINATION
transmission lines. Matched impedance techniques should be
used to maximize operating frequency and minimize signal dis-
tortion.
Figures 4A and 4B show two different layouts which are
recommended only as guidelines. Other suitable clock layouts
may exist and it would be recommended that the board design-
ers simulate to guarantee compatibility across all printed circuit
and clock component process variations.
V
CC - 2V
50
Ω
50
Ω
RTT
Z
o = 50Ω
Z
o = 50Ω
FOUT
FIN
RTT =
Z
o
1
((V
OH + VOL) / (VCC – 2)) – 2
3.3V
125
Ω
125
Ω
84
Ω
84
Ω
Z
o = 50Ω
Z
o = 50Ω
FOUT
FIN
相关PDF资料
PDF描述
CDB53L21 BOARD EVAL FOR CS53L21 ADC
MLG1005S36NJ INDUCTOR MULTILAYER 36NH 0402
EBM28DSES-S243 CONN EDGECARD 56POS .156 EYELET
CDB5346 BOARD EVAL FOR CS5346
CDB5345 EVALUATION BOARD FOR CS5345
相关代理商/技术参数
参数描述
CRD5463PM 功能描述:电源管理IC开发工具 Ref Design for Power Meter/Monitor RoHS:否 制造商:Maxim Integrated 产品:Evaluation Kits 类型:Battery Management 工具用于评估:MAX17710GB 输入电压: 输出电压:1.8 V
CRD5463PM-Z 功能描述:REFERENCE DESIGN FOR POWER METER RoHS:否 类别:编程器,开发系统 >> 评估演示板和套件 系列:- 标准包装:1 系列:PSoC® 主要目的:电源管理,热管理 嵌入式:- 已用 IC / 零件:- 主要属性:- 次要属性:- 已供物品:板,CD,电源
CRD5490-Z 功能描述:电源管理IC开发工具 CS5463 Pwr Meas/Mntr Reference Design RoHS:否 制造商:Maxim Integrated 产品:Evaluation Kits 类型:Battery Management 工具用于评估:MAX17710GB 输入电压: 输出电压:1.8 V
CRD5AS-12B 制造商:RENESAS 制造商全称:Renesas Technology Corp 功能描述:Reverse Conducting Thyristor Medium Power Use
CRD5AS-12B#B00 功能描述:SCR 600V 7.8A Sensitive Gate Surface Mount MP-3A 制造商:renesas electronics america 系列:- 包装:管件 零件状态:有效 电压 - 断态:600V 电压 - 栅极触发(Vgt)(最大值):800mV 电流 - 栅极触发(Igt)(最大值):100μA 电压 - 通态(Vtm)(最大值):1.8V 电流 - 通态(It(AV))(最大值):5A 电流 - 通态(It(RMS))(最大值):7.8A 电流 - 保持(Ih)(最大值):3mA 电流 - 断态(最大值):2mA 电流 - 不重复浪涌 50,60Hz(Itsm):90A @ 60Hz SCR 类型:灵敏栅极 工作温度:-40°C ~ 150°C 安装类型:表面贴装 封装/外壳:TO-252-3,DPak(2 引线+接片),SC-63 供应商器件封装:MP-3A 标准包装:1