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参数资料
| 型号： | CS2001YDWF20 |
| 元件分类： | 稳压器 |
| 英文描述： | SWITCHED CAPACITOR REGULATOR, 165 kHz SWITCHING FREQ-MAX, PDSO20 |
| 封装： | 0.300 INCH, SO-20 |
| 文件页数： | 4/5页 |
| 文件大小： | 138K |
| 代理商： | CS2001YDWF20 |
CS2001
4
Package Pin Description
PACKAGE PIN #
PIN SYMBOL
FUNCTION
20 Lead SO Wide
(internally fused leads)
1
VER
Energy reserve input.
2VBAT
Battery input.
3VFB
Charge PUMP control voltage input.
4
Gnd1
Ground.
5
Gnd2
Ground.
6
Gnd3
Ground.
7
Gnd4
Ground.
8VSW
Charge PUMP switch collector.
9
SWSD
Charge PUMP shutdown input.
10
COMP
Charge PUMP compensation pin.
11
CPUMP
Charge PUMP timing cap input.
12
IBIAS
Reference current resistor pin.
13
VCHG
Switched cap voltage tripler output.
14
Gnd5
Ground.
15
Gnd6
Ground.
16
Gnd7
Ground.
17
Gnd8
Ground.
18
NERD
No energy reserve detected output.
19
RESETB
Reset output.
20
VOUT
Linear regulator output.
Circuit Description
Figure 1. Typical operation with IVER = 30mA.
Figure 2. Startup with RV(CHG) = 510k.
Figure 1 is an oscilloscope waveform showing the charge
pump collector voltage, collector current and the charge
pump timing capacitor during normal operation with
IVER = 30mA.
Figure 2 is an oscilloscope waveform showing the
voltage tripler output and the energy reserve input during
power up.
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