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参数资料
型号： CS2200P-DZZR
厂商： CIRRUS LOGIC INC
元件分类： PLL合成/DDS/VCOs
中文描述： PHASE LOCKED LOOP, 56 MHz, PDSO10
封装： 3 MM, LEAD FREE, MO-187, MSOP-10
文件页数： 12/24页
文件大小： 177K
代理商： CS2200P-DZZR
CS2200-OTP
DS842F2
2
TABLE OF CONTENTS
1. PIN DESCRIPTION ................................................................................................................................. 4
2. TYPICAL CONNECTION DIAGRAM ..................................................................................................... 5
3. CHARACTERISTICS AND SPECIFICATIONS ...................................................................................... 6
RECOMMENDED OPERATING CONDITIONS .................................................................................... 6
ABSOLUTE MAXIMUM RATINGS ........................................................................................................ 6
DC ELECTRICAL CHARACTERISTICS ................................................................................................ 6
AC ELECTRICAL CHARACTERISTICS ................................................................................................ 7
4. ARCHITECTURE OVERVIEW ............................................................................................................... 8
4.1 Delta-Sigma Fractional-N Frequency Synthesizer ........................................................................... 8
5. APPLICATIONS ..................................................................................................................................... 9
5.1 One Time Programmability .............................................................................................................. 9
5.2 Timing Reference Clock Input .......................................................................................................... 9
5.2.1 Internal Timing Reference Clock Divider ................................................................................. 9
5.2.2 Crystal Connections (XTI and XTO) ...................................................................................... 10
5.2.3 External Reference Clock (REF_CLK) .................................................................................. 10
5.3 Output to Input Frequency Ratio Configuration ............................................................................. 11
5.3.1 User Defined Ratio (RUD) ..................................................................................................... 11
5.3.2 Ratio Modifier (R-Mod) .......................................................................................................... 11
5.3.3 Effective Ratio (REFF) .......................................................................................................... 11
5.3.4 Ratio Configuration Summary ............................................................................................... 12
5.4 PLL Clock Output ........................................................................................................................... 13
5.5 Auxiliary Output .............................................................................................................................. 14
5.6 Mode Pin Functionality ................................................................................................................... 14
5.6.1 M1 and M0 Mode Pin Functionality ....................................................................................... 14
5.6.2 M2 Mode Pin Functionality .................................................................................................... 15
5.6.2.1 M2 Configured as Output Disable .............................................................................. 15
5.6.2.2 M2 Configured as R-Mod Enable .............................................................................. 15
5.6.2.3 M2 Configured as AuxOutSrc Override ..................................................................... 15
5.7 Clock Output Stability Considerations ............................................................................................ 16
5.7.1 Output Switching ................................................................................................................... 16
5.7.2 PLL Unlock Conditions .......................................................................................................... 16
5.8 Required Power Up Sequencing for Programmed Devices ........................................................... 16
6. PARAMETER DESCRIPTIONS ........................................................................................................... 17
6.1 Modal Configuration Sets ............................................................................................................... 17
6.1.1 R-Mod Selection (RModSel[1:0]) ...........................................................................................17
6.1.2 Auxiliary Output Source Selection (AuxOutSrc[1:0]) ............................................................. 18
6.2 Ratio 0 - 3 ...................................................................................................................................... 18
6.3 Global Configuration Parameters ................................................................................................... 18
6.3.1 AUX PLL Lock Output Configuration (AuxLockCfg) .............................................................. 18
6.3.2 Reference Clock Input Divider (RefClkDiv[1:0]) .................................................................... 18
6.3.3 Enable PLL Clock Output on Unlock (ClkOutUnl) ................................................................. 19
6.3.4 M2 Pin Configuration (M2Config[2:0]) ................................................................................... 19
7. CALCULATING THE USER DEFINED RATIO .................................................................................... 20
7.1 12.20 Format .................................................................................................................................. 20
8. PROGRAMMING INFORMATION ........................................................................................................ 21
9. PACKAGE DIMENSIONS .................................................................................................................... 22
THERMAL CHARACTERISTICS ......................................................................................................... 22
10. ORDERING INFORMATION .............................................................................................................. 23
11. REVISION HISTORY .......................................................................................................................... 23
LIST OF FIGURES
Figure 1. Typical Connection Diagram ........................................................................................................ 5
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