参数资料
| 型号： | CS3310-KSZR |
| 厂商： | Cirrus Logic Inc |
| 文件页数： | 5/10页 |
| 文件大小： | 0K |
| 描述： | IC DGTL VOL CTRL 2CH 16-SOIC |
| 标准包装： | 1,000 |
| 类型： | 音量控制 |
| 应用： | 音频系统 |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 16-SOIC（0.295"，7.50mm 宽） |
| 供应商设备封装： | 16-SOIC |
| 包装： | 带卷 (TR) |
| 配用： | 598-1000-ND - BOARD EVAL FOR CS3310 COL CTRL |
Micrel, Inc.
SY89645L
June 2011
5
M9999-060711
hbwhelp@micrel.com
AC Electrical Characteristics
(5)
VCC = +3.3V ±5%, RL = 100 across the outputs, TA = –40°C to +85°C, unless otherwise stated.
Symbol
Parameter
Condition
Min.
Typ.
Max.
Units
fMAX
Maximum Frequency
VOUT > 140mV
650
MHz
tPD
Propagation Delay
fMAX ≤ 650MHz, Note 6
1.0
1.8
3.0
ns
Output Skew
Note 7
40
ps
tSKEW
Part-to-Part Skew
Note 8
500
ps
tr, tf
Output Rise/Fall Times
(20% to 80%)
fMAX ≤ 266MHz
150
250
400
ps
fMAX ≤ 266MHz
45
55
%
Duty Cycle
fMAX > 266MHz
40
60
%
Notes:
5.
All parameters measured at fMAX ≤ 650MHz, unless otherwise stated.
6.
Measured from VCC/2 of the input to the differential output crossing point.
7.
Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VCC/2 of the input to the differential
output crossing point.
8.
Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. Using the same type
of inputs on each device, the outputs are measured at the differential cross points.
Timing Diagram
Clock Enable (CLK_EN) Description
The enable function is synchronous so that the clock
outputs will be enabled or disabled following a rising and
a falling edge of the input clock.
or (408) 955-1690
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