参数资料
型号: CS3865CGDWR16
厂商: ON SEMICONDUCTOR
元件分类: 稳压器
英文描述: 1 A DUAL SWITCHING CONTROLLER, 500 kHz SWITCHING FREQ-MAX, PDSO16
封装: 0.300 INCH, MS-013, SO-16
文件页数: 7/8页
文件大小: 82K
代理商: CS3865CGDWR16
7
High frequency circuit layout techniques are imperative to
prevent pulse-width jitter. This is usually caused by exces-
sive noise pick-up imposed on the current sense and volt-
age feed-back inputs. Noise immunity can be improved by
lowering circuit impedances at these points. The printed
circuit board layout should contain a ground plane with
low current signal and high current switch and output
grounds returning on separate paths back to the input fil-
ter capacitor. Ceramic bypass capacitors (0.1F) connected
directly to VCC and VREF may be required to improve noise
filtering. They provide a low impedance path for filtering
the high frequency noise. All high current loops should be
kept as short as possible using heavy copper runs. The
error amp compensation circuitry and the converter out-
put voltage-divider should be located close to the IC and
as far as possible from the power switch and other noise
generating components.
Design Considerations
Operating Description: continued
+
-
+
-
+
-
+
-
+
-
+
-
RT
CT
VFB
1
Reference
Regulator
VREF
UVLO
3.4V
14V
2.5V
R
20k
VREF
Sync
1.0mA
2R
0.5V
250
A
R
1.0mA
2R
Error
Amp 2
COMP1
ENABLE2
VFB
2
COMP2
Gnd
Pwr Gnd
R
0.5V
Current Sense
Comparator 1
Current Sense
Comparator 1
R
S
Q
R
S
R
PWM
Latch 2
PWM
Latch 1
VCC
UVLO
VCC
17V
VIN
VOUT1
VOUT2
Sense1
Q1
Q2
RSense1
Sense2
RSense2
+
-
+
-
Error
Amp 1
VOUT
1
VOUT
2
COUT
2
COUT
1
5.0V
Q
Oscillator
Internal
Bias
CF1 +
L1
D1
L2
D2
+
CF2
RFB
1
RFB
2
RFB
3
RFB
4
VOUT
2
VOUT
1
Dual Boost Regulator
Applications Diagram
CS3865C
SYNC
CT
Latch 1
“Set” Input
COMP1
Sense1
VOUT1
Latch 1
“Reset” Input
ENABLE2
Latch 2
“Set” Input
COMP2
Sense2
Latch 2
“Reset” Input
VOUT2
0V
Timing Diagram
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