参数资料
型号: CS4192XDWFR16
厂商: ON SEMICONDUCTOR
元件分类: 外设及接口
英文描述: Single Air-Core Gauge Driver
中文描述: HALF BRIDGE BASED PRPHL DRVR, PDSO16
封装: SOIC-16
文件页数: 4/8页
文件大小: 71K
代理商: CS4192XDWFR16
CS4192
http://onsemi.com
4
PIN FUNCTION DESCRIPTION
PACKAGE PIN #
PIN SYMBOL
FUNCTION
16 Lead SO Wide
1
SIN–
Negative output for SINE coil.
2
SIN+
Positive output SINE coil.
3
V
BB
Analog supply. Nominally 13.5 V.
4, 5, 12, 13
GND
Ground.
6
SI
Serial data input. Data present at the rising edge of the clock
signal is shifted into the internal shift register.
7
V
CC
5.0 V logic supply. The internal registers and latches are
reset by a POR generated by the rising edge of the voltage
on this pin.
8
OE
Controls the state of the output buffers. A logic low on this
pin turns them off.
9
SCLK
Serial clock for shifting in/out of data. Rising edge shifts data
on SI into the shift register and the falling edge changes the
data on SO.
10
CS
When high allows data at SI to be shifted into part with the
rising edges of SCLK. The falling edge transfers the shift
register contents into the DAC and multiplexer to update the
output buffers. The falling edge also reenables the output
drivers if they have been disabled by a fault.
11
ST
STATUS reflects the state of the outputs and is low anytime
the outputs are disabled, either by OE or the internal protec-
tion circuitry. Requires external pull–up resistor.
14
SO
Serial data output. Existing 10–bit data is shifted out when
new data is shifted in. Allows cascading of multiple devices
on common serial port.
15
COS–
Negative output for COSINE coil.
16
COS+
Positive output for COSINE coil.
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