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参数资料
| 型号： | CS4207-CNZ |
| 厂商： | Cirrus Logic Inc |
| 文件页数： | 18/77页 |
| 文件大小： | 0K |
| 描述： | IC CODEC AUD HDPN AMP COMM 48QFN |
| 标准包装： | 429 |
| 类型： | 音频编解码器 |
| 数据接口： | 串行 |
| 分辨率（位）： | 24 b |
| ADC / DAC 数量： | 2 / 3 |
| 三角积分调变： | 是 |
| 动态范围，标准 ADC / DAC (db)： | 105 / 110 |
| 电压 - 电源，模拟： | 2.97 V ~ 5.25 V |
| 电压 - 电源，数字： | 2.97 V ~ 5.25 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 48-QFN |
| 供应商设备封装： | 48-QFN-EP（6x6） |
| 包装： | 托盘 |
| 其它名称： | 598-1796 |
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DS880F4
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CS4207
4. CODEC RESET AND INITIALIZATION
4.1
Link Reset
A Link Reset is a system controller generated assertion of the HD Audio Bus RESET# signal. A Link reset
will cause some of the HD Audio bus interface logic to be initialized. Following a Link Reset, the CS4207
will perform the Codec Initialization request sequence. Many of the codec settings will remain unchanged
following a Link Reset. See “Register Settings Across Reset Conditions” section on page 29 for more de-
tails.
When the codec has detected a Link Reset condition, all converter widgets and pin widgets will transition to
a low power operating mode, if previously in D0. The actual power states reported will remain unchanged,
i.e. if in D0 or D3 prior to Link Reset, the widget stays in D0 or D3. If enabled, presence detection will con-
tinue to sense any impedance changes and issue a power state change request to the Link prior to asserting
an Unsolicited Response.
4.2
Function Group Reset
Because the CS4207 supports the Extended Power State Support (EPSS), a single occurrence of the
Func-
tion Group Reset command will NOT cause the Audio Function unit and all associated widgets to initialize
to the power-on reset values (as described in the HD Audio Specification, Rev. 1.0). When the CS4207 re-
ceives a single Function Group Reset verb, the codec will issue a response to the verb to acknowledge re-
ceipt, and reset each input/output converter widget’s Stream Number and Lowest Channel Number to the
default (0h). No other settings are modified. See “Register Settings Across Reset Conditions” section on
page 29 for more details.
The CS4207 will respond to the newly created “Double Function Group Reset” (as defined in HDA015-B,
March 1, 2007) and will reset most of the register settings to their power on defaults. This “Double Function
Group Reset” will not affect the HD Audio bus interface logic or the unique codec physical address, which
must be reset with the link RESET# signal. Therefore, the codec will not initiate a Codec Initialization se-
quence on the link. In addition, the Configuration Default settings will not be reset with a “Double Function
Group Reset”.
This new reset condition is created by sending two Function Group resets back to back. The “Double Func-
tion Group Reset” is defined as two (2) Function Group Reset verbs received without any other intervening
verbs. The Function Group Reset verbs are not required to be received in sequential frames, but there must
not be any other verbs received in frames between the receipt of the Function Group Reset verbs. There
are no implied time outs between the time the first Function Group Reset is received and the second Func-
tion Group Reset verb.
4.3
Codec Initialization
Immediately following the completion of a Link Reset sequence, the CS4207 will initiate a codec initialization
sequence. The purpose of this initialization sequence is to acquire a unique address by which the codec
can thereafter be referenced with Commands on the SDO signal. During this sequence, the Controller pro-
vides the codec with a unique address using its attached SDI signal.
If the CS4207 codec is in a low power D3 state and enabled to support a presence detect event, it will retain
its unique address while in that low power state. If RESET# is de-asserted high, and BITCLK and SYNC are
running at the time of a presence detect event, the codec will signal an unsolicited response.
When put into the D3 low power state and enabled to support a presence detect event, with the link in the
reset state (RESET# is asserted low), the CS4207 will post the occurrence of a wake event and request a
power state change by signaling a power state change request and initialization request. It will reestablish
the connection with the controller by performing a “Codec Initialization request”.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| CS4207-CNZ/C1 | 制造商:CIRRUS 制造商全称:Cirrus Logic 功能描述:Low-power, 4-in / 6-out HD Audio CODEC with Headphone Amp |
| CS4207-CNZR | 功能描述:接口—CODEC IC Lo Pwr,4/6 HD Aud Codec w/HP Amp RoHS:否 制造商:Texas Instruments 类型: 分辨率: 转换速率:48 kSPs 接口类型:I2C ADC 数量:2 DAC 数量:4 工作电源电压:1.8 V, 2.1 V, 2.3 V to 5.5 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:DSBGA-81 封装:Reel |
| CS4207-CNZR/C1 | 制造商:CIRRUS 制造商全称:Cirrus Logic 功能描述:Low-power, 4-in / 6-out HD Audio CODEC with Headphone Amp |
| CS4207-DNZ | 功能描述:接口—CODEC IC Lo Pwr,4/6 HD Aud Codec w/HP Amp RoHS:否 制造商:Texas Instruments 类型: 分辨率: 转换速率:48 kSPs 接口类型:I2C ADC 数量:2 DAC 数量:4 工作电源电压:1.8 V, 2.1 V, 2.3 V to 5.5 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:DSBGA-81 封装:Reel |
| CS4207-DNZR | 功能描述:接口—CODEC IC Lo Pwr,4/6 HD Aud Codec w/HP Amp RoHS:否 制造商:Texas Instruments 类型: 分辨率: 转换速率:48 kSPs 接口类型:I2C ADC 数量:2 DAC 数量:4 工作电源电压:1.8 V, 2.1 V, 2.3 V to 5.5 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:DSBGA-81 封装:Reel |
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