参数资料
型号: CS4341A-KSZ
厂商: Cirrus Logic Inc
文件页数: 9/34页
文件大小: 0K
描述: IC DAC STER 24BIT 192KHZ 16SOIC
标准包装: 48
位数: 24
数据接口: 串行
转换器数目: 2
电压电源: 单电源
功率耗散(最大): 90mW
工作温度: -10°C ~ 70°C
安装类型: 表面贴装
封装/外壳: 16-SOIC(0.154",3.90mm 宽)
供应商设备封装: 16-SOIC
包装: 托盘
输出数目和类型: 2 电压,单极
采样率(每秒): 192k
产品目录页面: 756 (CN2011-ZH PDF)
其它名称: 598-1633
CS4341A
DS582F2
17
5.
REGISTER DESCRIPTION
NOTE: All registers are read/write in I2C mode and write only in SPI mode, unless otherwise stated.
5.1
MODE CONTROL 1 (ADDRESS 00H)
5.1.1 SPEED MODE CONTROL (MC) BIT 5-6
Default = 00
00 - Single-Speed Mode
01 - Double-Speed Mode
10 - Quad-Speed Mode
The operational speed mode must be set if the auto-detect defeat bit is enabled (AUTOD = 1). These
bits are ignored if the auto-detect defeat is disabled (AUTOD = 0).
5.1.2 AUTO-DETECT DEFEAT (AUTOD) BIT 2
Default = 0
0 - Disabled
1 - Enabled
The Auto-Detect function can be defeated to allow sample rate changes from 50 to 84 kHz, and from
100 to 170 kHz. The operational speed mode must be set via the speed mode control bits (see section
5.1.1) if the auto-detect feature is defeated.
5.1.3 MCLK DIVIDE-BY-2 (MCLKDIV) BIT 1
Default = 0
0 - Disabled
1 - Enabled
Function:
The MCLKDIV bit enables a circuit which divides the externally applied MCLK signal by 2.
5.2
MODE CONTROL 2 (ADDRESS 01H)
7
654
32
10
Reserved
MC1
MC0
Reserved
AUTOD
MCLKDIV
Reserved
0
000
00
7
654
32
10
AMUTE
DIF2
DIF1
DIF0
DEM1
DEM0
POR
PDN
1
000
00
11
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