参数资料
型号: CS4360-DZZR
厂商: Cirrus Logic Inc
文件页数: 16/37页
文件大小: 0K
描述: IC DAC STER 6CH 102DB 28-TSSOP
标准包装: 4,000
位数: 24
数据接口: 串行
转换器数目: 6
电压电源: 模拟和数字
功率耗散(最大): 265mW
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 28-TSSOP(0.173",4.40mm 宽)
供应商设备封装: 28-TSSOP
包装: 带卷 (TR)
输出数目和类型: 6 电压,单极
采样率(每秒): 192k
CS4360
DS517F2
23
4.3.2
Control Port Mode
The desired format is selected via the DIF2, DIF1 and DIF0 bits in the Mode Control 2 register (see section
6.1.2). For an illustration of the required relationship between LRCK, SCLK and SDIN, see Figures 15-17.
4.4
De-Emphasis Control
The device includes on-chip digital de-emphasis. Figure 18 shows the de-emphasis curve for Fs equal to
44.1 kHz. The frequency response of the de-emphasis curve will scale proportionally with changes in
sample rate, Fs.
Notes: De-emphasis is only available in Single-speed Mode.
LR C K
SC L K
Left C hannel
R ig ht C hannel
SD IN
+3 +2 +1
+5 +4
MS B
-1 - 2 -3 -4 -5
+3 +2 +1
+5 +4
-1 -2 -3 -4
LS B
MS B
LS B
Figure 15. Left Justified up to 24-Bit Data
LR C K
SC L K
Left C hannel
R ig ht C hannel
SD IN
+3 +2 +1
+5 +4
MS B
-1 - 2 -3 -4 -5
+3 +2 +1
+5 +4
-1 -2 - 3 -4
MS B
LS B
Figure 16. I2S, up to 24-Bit Data
LRCK
SC LK
Left C hannel
SDIN
+6 +5 +4 +3
+2 +1
+7
-1 -2 -3 -4 -5
LS B
Right Cha nnel
MSB
LS B
+6 +5 +4 +3 +2 +1
+7
-1 -2 -3 -4 -5
MSB
LSB
Figure 17. Right Justified Data
Gain
dB
-10dB
0dB
Frequency
T2 = 15 s
T1=50 s
F1
F2
3.183 kHz
10.61 kHz
Figure 18. De-emphasis Curve
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