参数资料
| 型号： | CS4362A-DQZ |
| 厂商： | Cirrus Logic Inc |
| 文件页数： | 6/13页 |
| 文件大小： | 0K |
| 描述： | IC DAC 6CH 114DB 192KHZ 48-LQFP |
| 标准包装： | 250 |
| 位数： | 24 |
| 数据接口： | 串行 |
| 转换器数目： | 6 |
| 电压电源： | 模拟和数字 |
| 功率耗散（最大）： | 390mW |
| 工作温度： | -40°C ~ 105°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 48-LQFP |
| 供应商设备封装： | 48-LQFP（7x7） |
| 包装： | 托盘 |
| 输出数目和类型： | 6 电压，单极 |
| 采样率（每秒）： | 192k |
| 配用： | 598-1521-ND - BOARD EVAL FOR CS4362A DAC |
2
ICS97U870
Advance Information
0817—07/07/03
Pin Descriptions
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The PLL clock buffer, ICS97U870, is designed for a VDDQ of 1.8 V, a AVDD of 1.8 V and differential data input and output
levels. Package options include a plastic 52-ball VFBGA and a 40-pin MLF.
ICS97U870 is a zero delay buffer that distributes a differential clock input pair (CLK_INT, CLK_INC) to ten differential
pair of clock outputs (CLKT[0:9], CLKC[0:9]) and one differential pair feedback clock outputs (FB_OUTT, FBOUTC).
The clock outputs are controlled by the input clocks (CLK_INT, CLK_INC), the feedback clocks (FB_INT, FB_INC), the
LVCMOS program pins (OE, OS) and the Analog Power input (AVDD).When OE is low, the outputs (except FB_OUTT/
FB_OUTC) are disabled while the internal PLL continues to maintain its locked-in frequency. OS (Output Select) is a
program pin that must be tied to GND or VDDQ.When OS is high, OE will function as described above.When OS is low,
OE has no effect on CLKT7/CLKC7 (they are free running in addition to FB_OUTT/FB_OUTC).When AVDD is grounded,
the PLL is turned off and bypassed for test purposes.
When both clock signals (CLK_INT, CLK_INC) are logic low, the device will enter a low power mode. An input logic
detection circuit on the differential inputs, independent from the input buffers, will detect the logic low level and perform
a low power state where all outputs, the feedback and the PLL are OFF.When the inputs transition from both being logic
low to being differential signals, the PLL will be turned back on, the inputs and outputs will be enabled and the PLL
will obtain phase lock between the feedback clock pair (FB_INT, FB_INC) and the input clock pair (CLK_INT, CLK_INC)
within the specified stabilization time tSTAB.
The PLL in ICS97U870 clock driver uses the input clocks (CLK_INT, CLK_INC) and the feedback clocks (FB_INT,
FB_INC) to provide high-performance, low-skew, low-jitter output differential clocks (CLKT[0:9], CLKC[0:9]).ICS97U870
is also able to track Spread Spectrum Clocking (SSC) for reduced EMI.
ICS97U870 is characterized for operation from 0°C to 70°C.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| CS4362A-DQZR | 功能描述:数模转换器- DAC IC 114dB 192 kHz 6Chn DAC w/DSD supt RoHS:否 制造商:Texas Instruments 转换器数量:1 DAC 输出端数量:1 转换速率:2 MSPs 分辨率:16 bit 接口类型:QSPI, SPI, Serial (3-Wire, Microwire) 稳定时间:1 us 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:SOIC-14 封装:Tube |
| CS4362A-EQZ | 制造商:CIRRUS 制造商全称:Cirrus Logic 功能描述:114 dB, 192 kHz 6-channel D/A Converter |
| CS4362A-EQZR | 制造商:CIRRUS 制造商全称:Cirrus Logic 功能描述:114 dB, 192 kHz 6-channel D/A Converter |
| CS4362-BQ | 制造商:CIRRUS 制造商全称:Cirrus Logic 功能描述:114 dB, 192 kHz 6-Channel D/A Converter |
| CS4362-KQ | 制造商:Cirrus Logic 功能描述:114 DB, 24-BIT, 192 KHZ, 6- & 8-CHANNEL D/A CONVERTER - Rail/Tube |
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