参数资料
型号: CS4391A-KZZR
厂商: Cirrus Logic Inc
文件页数: 13/40页
文件大小: 0K
描述: IC DAC 24BIT 192KHZ W/VC 20TSSOP
标准包装: 4,000
位数: 24
数据接口: 串行
转换器数目: 2
电压电源: 单电源
功率耗散(最大): 175mW
工作温度: -10°C ~ 70°C
安装类型: 表面贴装
封装/外壳: 20-TSSOP(0.173",4.40mm 宽)
供应商设备封装: 20-TSSOP
包装: 带卷 (TR)
输出数目和类型: 4 电压,单极
采样率(每秒): 192k
CS4391A
20
DS600PP3
4.4
CHANNEL B VOLUME CONTROL - ADDRESS 04H
4.4.1
Mute (Bit 7)
Function:
The Digital-to-Analog converter output will mute when enabled. The common mode voltage on the
output will be retained. The muting function is effected, similiar to attenuation changes, by the Soft
and Zero Cross bits in the Volume and Mixing Control register. The MUTEC pin for that channel will
go active during the mute period if the Mute function is enabled. Both the AMUTEC and BMUTEC
will go active if either MUTE register is enabled and the MUTEC A = B bit (register 5) is enabled.
4.4.2
Volume Control (Bits 6:0)
Function:
The digital volume control allows the user to attenuate the signal in 1 dB increments from 0 to -119 dB.
Volume settings are decoded as shown in Table 7. The volume changes are implemented as dictated
by the Soft and Zero Cross bits in the Volume and Mixing Control register. All volume settings less
than -119 dB are equivalent to enabling the Mute bit.
4.5
MODE CONTROL 2 - ADDRESS 05H
4.5.1
Invert Signal Polarity (Bits 7:6)
Function:
When set, this bit inverts the signal polarity.
4.5.2
Control Port Enable (Bit 5)
Function:
This bit defaults to 0, allowing the device to power-up in Stand-Alone mode. The Control port mode
can be accessed by setting this bit to 1. This will allow the operation of the device to be controlled by
the registers and the pin definitions will conform to Control Port Mode. To accomplish a clean and
click free power-up, the user should write 30h to register 5 within 10 ms following the release of Reset.
4.5.3
Power Down (Bit 4)
Function:
The device will enter a low-power state whenever this function is activated. The power-down bit de-
faults to ‘enabled’ on power-up and must be disabled before normal operation will begin. The contents
of the control registers are retained when the device is in power-down.
4.5.4
AMUTEC = BMUTEC (Bit 3)
Function:
When this function is enabled, the individual controls for AMUTEC and BMUTEC are internally con-
nected through a AND gate prior to the output pins. Therefore, the external AMUTEC and BMUTEC
pins will go active only when the requirements for both AMUTEC and BMUTEC are valid.
76543
210
MUTE
VOL6
VOL5
VOL4
VOL3
VOL2
VOL1
VOL0
76543
210
INVERT_A
INVERT_B
CPEN
PDN
MUTEC A = B
FREEZE
MCLK Divide
Reserved
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