参数资料
| 型号： | CS4461-CZZR |
| 厂商： | Cirrus Logic Inc |
| 文件页数： | 11/11页 |
| 文件大小： | 0K |
| 描述： | IC ADC PSR FEEDBACK 24-TSSOP |
| 标准包装： | 2,000 |
| 采样率（每秒）： | 7.5M |
| 数据接口： | 串行 |
| 转换器数目： | 1 |
| 功率耗散（最大）： | 235mW |
| 电压电源： | 模拟和数字 |
| 工作温度： | -10°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 24-TSSOP（0.173"，4.40mm 宽） |
| 供应商设备封装： | 24-TSSOP |
| 包装： | 带卷 (TR) |
| 输入数目和类型： | 1 个差分，单极 |
DS650F1
9
CS4461
4.3
Power-Up Sequence
Reliable power-up can be accomplished by keeping the device in reset until the power supplies and clocks
are stable. It is also recommended that reset be enabled if the analog or digital supplies drop below the min-
imum specified operating voltages to prevent power glitch related issues.
The internal reference voltage must be stable for the device to produce valid data. Therefore, there is a de-
lay between the release of reset and the generation of valid output, due to the finite output impedance of
FILT+ and the presence of the external capacitance.
4.4
Overflow Detection
The CS4461 includes modulator overflow detection, indicated on pin 15, OVERFLOW (open drain, active
low). OVERFLOW will go to a logical low as soon as an overrange condition is detected. The data will re-
main low until the condition is cleared.
4.5
Grounding and Power Supply Decoupling
As with any high resolution converter, the CS4461 requires careful attention to power supply and grounding
arrangements if its potential performance is to be realized. Figure 1 shows the recommended power ar-
rangements, with VA and VDP connected to clean supplies. VDP, which powers the digital logic, may be
run from the system logic supply or may be powered from the analog supply via a resistor. In this case, no
additional devices should be powered from VDP. Decoupling capacitors should be as near to the ADC as
possible, with the low value ceramic capacitor being the nearest. All signals, especially clocks, should be
kept away from the FILT+ and VQ pins in order to avoid unwanted coupling into the modulator. The FILT+
and VQ decoupling capacitors, particularly the 0.1 F, must be positioned to minimize the electrical path
from FILT+ to GND. The CDB44800 evaluation board demonstrates the optimum layout and power supply
arrangements. To minimize digital noise, connect the ADC digital outputs only to CMOS inputs.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| CS4461-DZZ | 制造商:Cirrus Logic 功能描述:ADC SGL DELTA-SIGMA 7.5MSPS SERL 24TSSOP - Rail/Tube |
| CS4461-DZZR | 制造商:Cirrus Logic 功能描述:ADC SGL DELTA-SIGMA 7.5MSPS SERL 24SSOP - Tape and Reel |
| CS4468A3 | 制造商:HVPSI 制造商全称:High Voltage Power Solutions, Inc. 功能描述:180 KV RECTIFIER |
| CS4473-000 | 制造商:TE Connectivity 功能描述:MTC100-JA2-P11M2-CS082 - Bulk |
| CS4474-000 | 制造商:TE Connectivity 功能描述:Connector Accessories Socket Insert 制造商:TE Connectivity 功能描述:MTC100-JA2-S11M2-CS082 - Bulk |
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