参数资料
型号: CS495314-DVZ
厂商: Cirrus Logic Inc
文件页数: 10/19页
文件大小: 0K
描述: IC DSP DECODER 32BIT 128-LQFP
标准包装: 72
系列: *
其它名称: 598-1944
CS4953xx Data Sheet
32-bit Audio Decoder DSP Family
DS705F2
18
5.13 Switching Characteristics — Serial Control Port - I2C Master Mode
Figure 6. Serial Control Port - I2C Master Mode Timing
Parameter
Symbol
Min
Max
Units
SCP_CLK frequency1
1. The specification fiicck indicates the maximum speed of the hardware. The system designer should be aware that
the actual maximum speed of the communication port may be limited by the firmware application.
fiicck
400
kHz
SCP_CLK low time
tiicckl
1.25
s
SCP_CLK high time
tiicckh
1.25
s
SCP_SCK rising to SCP_SDA rising or falling for START or STOP
condition
tiicckcmd
1.25
s
START condition to SCP_CLK falling
tiicstscl
1.25
s
SCP_CLK falling to STOP condition
tiicstp
2.5
s
Bus free time between STOP and START conditions
tiicbft
3—
s
Setup time SCP_SDA input valid to SCP_CLK rising
tiicsu
100
ns
Hold time SCP_SDA input after SCP_CLK falling2
2. This parameter is measured from the ViL level at the falling edge of the clock.
tiich
0—
ns
SCP_CLK low to SCP_SDA out valid
tiicdov
—36
ns
SCP_CLK
SCP_SDA
0
1
67
80
1
7
tiicckl
tiicckh
tiicsu
tiich
A6
A0
R/W
ACK
LSB
8
ACK
MSB
tiicstp
6
tiicdov
tiicbft
tiicstscl
tiicckcmd
fiicck
tiicckcmd
tiicf
tiicr
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