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| 型号： | CS5174GDR8G |
| 厂商： | ON Semiconductor |
| 文件页数： | 17/21页 |
| 文件大小： | 0K |
| 描述： | IC REG MULTI CONFIG 1.5A 8SOIC |
| 标准包装： | 1 |
| 类型： | 升压（升压），回扫，正向转换器，Sepic |
| 输出数： | 1 |
| 输入电压： | 2.7 V ~ 30 V |
| PWM 型： | 电流模式 |
| 频率 - 开关： | 560kHz |
| 电流 - 输出： | 1.5A |
| 同步整流器： | 无 |
| 工作温度： | 0°C ~ 125°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 8-SOIC（0.154"，3.90mm 宽） |
| 包装： | 标准包装 |
| 供应商设备封装： | 8-SOICN |
| 产品目录页面： | 1116 (CN2011-ZH PDF) |
| 其它名称： | CS5174GDR8GOSDKR |
CS5171, CS5172, CS5173, CS5174
TJ + TA ) (PD q JA)
where:
transitions that can cause problems. Therefore the following
guidelines should be followed in the layout.
T J = IC or FET junction temperature ( ° C);
T A = ambient temperature ( ° C);
P D = power dissipated by part in question (W);
q JA = junction ? to ? ambient thermal resistance ( ° C/W).
For the CS517x, q JA =165 ° C/W.
Once the designer has calculated T J , the question of
whether the CS517x can be used in an application is settled.
If T J exceeds 150 ° C, the absolute maximum allowable
junction temperature, the CS517x is not suitable for that
application.
If T J approaches 150 ° C, the designer should consider
possible means of reducing the junction temperature.
Perhaps another converter topology could be selected to
reduce the switch current. Increasing the airflow across the
surface of the chip might be considered to reduce T A .
Circuit Layout Guidelines
In any switching power supply, circuit layout is very
important for proper operation. Rapidly switching currents
combined with trace inductance generates voltage
1.
2.
3.
In boost circuits, high AC current circulates within the
loop composed of the diode, output capacitor, and
on ? chip power transistor. The length of associated
traces and leads should be kept as short as possible. In
the flyback circuit, high AC current loops exist on both
sides of the transformer. On the primary side, the loop
consists of the input capacitor, transformer, and
on ? chip power transistor, while the transformer,
rectifier diodes, and output capacitors form another
loop on the secondary side. Just as in the boost circuit,
all traces and leads containing large AC currents
should be kept short.
Separate the low current signal grounds from the
power grounds. Use single point grounding or ground
plane construction for the best results.
Locate the voltage feedback resistors as near the IC as
possible to keep the sensitive feedback wiring short.
Connect feedback resistors to the low current analog
ground.
C1
R2
4.87 k
1
2
V C
Test
V SW
PGND
8
7
C4
+
22 m F
D1
MBRS120T3
V OUT
? 12 V
SS
0.01 m F
SS
V CC
5.0 V
3 NFB
4
AGND
V CC
6
5
L1
22 m H
D2
MBRS120T3
+
C3
22 m F
R1
5.0 k
R3
1.27 k
+
C2
22 m F
Figure 41. Additional Application Diagram, 5.0 V to ? 12 V/ 75 mA Inverting Converter
http://onsemi.com
17
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