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| 型号： | CS5301GDW32G |
| 厂商： | ON Semiconductor |
| 文件页数： | 17/19页 |
| 文件大小： | 0K |
| 描述： | IC REG CTRLR BUCK PWM 32-SOIC |
| 产品变化通告： | Product Obsolescence 05/Oct/2010 |
| 标准包装： | 22 |
| PWM 型： | 电流/电压模式，V²? |
| 输出数： | 1 |
| 频率 - 最大： | 1MHz |
| 电源电压： | 4.7 V ~ 20 V |
| 降压： | 是 |
| 升压： | 无 |
| 回扫： | 无 |
| 反相： | 无 |
| 倍增器： | 无 |
| 除法器： | 无 |
| Cuk： | 无 |
| 隔离： | 无 |
| 工作温度： | 0°C ~ 70°C |
| 封装/外壳： | 32-SOIC（0.295"，7.50mm 宽） |
| 包装： | 管件 |
CS5301
3. For resistive current sensing choose L and R S to
provide a steady state ramp greater than 25 mV.
Adaptive Positioning
7. To set the amount of voltage positioning above the
L RS + (VIN * VOUT)
VOUT VIN
f 25 mV
DAC setting at no load connect a resistor (R VFB )
between the output voltage and the V FB pin. Choose
R VFB as;
Again the ratio of L and R L is fixed and the values of
L and R S will be a compromise.
4. Calculate the high frequency output impedance
(ConverterZ) of the converter during transients. This
is the impedance of the Output filter ESR in parallel
with the power stage output impedance (PwrstgZ)
and will indicate how far from the original level
( D VR) the output voltage will typically recover to
within one switching cycle. For a good transient
response D VR should be less than the peak output
voltage overshoot or undershoot.
D VR + ConverterZ IOUT
RVFB + NL Position VFB Bias Current
See Figure 4 for V FB Bias Current.
8. To set the difference in output voltage between no
load and full load, connect a resistor (R VDRP )
between the V DRP and V FB pins. R VDRP can be
calculated in two steps. First calculate the difference
between the V DRP and V FB pin at full load. (The V FB
voltage should be the same as the DAC voltage during
closed loop operation.) Then choose the R VDRP to
source enough current across R VFB for the desired
change in output voltage.
D VVDRP + R IOUT CS to VDRP Gain
ConverterZ +
where:
PwrstgZ ESR
PwrstgZ ) ESR
where:
R = R L or R S for one phase;
I OUT is the full load output current.
PwrstgZ + RS
CSA Gain 3
RVDRP + D VVDRP
RV(FB) D VOUT
Multiply the converterZ by the output current step
size to calculate where the output voltage should
recover to within the first switching cycle after a
transient. If the ConverterZ is higher than the value
required to recover to where the adaptive positioning
is set the remainder of the recovery will be controlled
by the error amp compensation and will typically
recover in 10?20 m s.
DESIGN EXAMPLE
Choose the component values for lossless current sensing,
adaptive positioning and current limit for a 250 kHz, 1.55 V,
60 A converter. The VID code is set to 1.6 V. Adaptive
positioning is set for 100 mV above DAC OUT (or 25 mV
below VID) at no load and 75 mV below the no load position
with a 60 A load. The peak output voltage transient should
be less than 100 mV during a 60 A step current. The
D VR + D IOUT
ConverterZ
overcurrent limit is nominally 75 A.
R + (VIN * VOUT)
+ (12 * 1.55)
Make sure that D VR is less than the expected peak
transient for a good transient response.
5. Adjust L and R L or R S as required to meet the best
combination of transient response, steady state output
voltage ripple and pulse width jitter.
Current Limit
When the sum of the Current Sense amplifiers (V ITOTAL )
exceeds the voltage on the I LIM pin the part will enter hiccup
mode. For inductive sensing the I LIM pin voltage should be
Current Sensing, Power Stage and
Output Filter Components
1. Assume 1.5 m W of output filter ESR.
2. Choose C + 0.01 m F
VOUT VIN
f C 25 mV
1.55 12
250 k 0.01 m F 25 mV
+ 21.5 k W ? Choose 20 k W
L RL + R C + 20 k W 0.01 m F + 200 m s
set based on the inductor resistance (or current sense
resistor) at max temperature and max current. To set the level
Choose RL + 2.0 m W
L + RL R C + 2.0 m W
200 m s + 400 nH
ConverterZ +
of the I LIM pin:
6. VILIM +
where:
R is R L or R S;
I OUT(LIM) is the current limit threshold.
For the overcurrent to work properly the inductor
time constant (L/R) should be ≤ the Current sense RC.
If the RC is too fast, during step loads the current
waveform will appear larger than it is (typically for a
few hundred m s) and may trip the current limit at a
3. n/a
4. PwrstgZ + RL CSA Gain 3
+ 2.0 m W 4.2 3.0 + 2.8 m W
PwrstgZ ESR
PwrstgZ ) ESR
+ 2.8 m W 1.5 m W ^ 1.0 m W
2.8 m W ) 1.5 m W
D VR + ConverterZ IOUT
+ 1.0 m W 60 A + 60 mV
5. n/a
level lower than the DC limit.
http://onsemi.com
17
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