参数资料
型号: CS5340-CZZ
厂商: Cirrus Logic Inc
文件页数: 5/10页
文件大小: 0K
描述: IC ADC AUD 101DB 200KHZ 16-TSSOP
标准包装: 96
位数: 24
采样率(每秒): 200k
数据接口: 串行
转换器数目: 2
电压电源: 单电源
工作温度: -10°C ~ 70°C
安装类型: 表面贴装
封装/外壳: 16-TSSOP(0.173",4.40mm 宽)
供应商设备封装: 16-TSSOP
包装: 管件
输入数目和类型: 2 个单端,单极
产品目录页面: 755 (CN2011-ZH PDF)
配用: 598-1544-ND - BOARD EVAL FOR CS5340 STEREO ADC
其它名称: 598-1081-5
Technical Note
4/21
www.rohm.com
2009.04 - Rev.A
2009 ROHM Co., Ltd. All rights reserved.
BU3071HFV,BU3072HFV,BU3073HFV,BU3076HFV,BU7322HFV,BU7325HFV
BU7322HFV(Ta=25℃, VDD=3.3V, Crystal frequency=27.0000MHz, unless otherwise specified.)
Parameter
Symbol
Limits
Unit
Conditions
Min.
Typ.
Max.
Output H voltage
VOH
2.8
-
V
IOH=-4.0mA
Output L voltage
VOL
-
0.5
V
IOL=4.0mA
Pull-down resistance
Rpd
25
50
100
k
Pull-down resistance on input pin
Consumption current 1
IDD
-
10
13.5
mA
49.5MHz output, at no load
Consumption current 2
IDD2
-
9.5
13.0
mA
36.0MHz output, at no load
Standby current
IDDst
-
1
A
OE=L
Output frequency
CLK_49.5
-
49.5000
-
MHz
SEL=L, IN*66/6/6
CLK_36
-
36.0000
-
MHz
SEL=H, IN*64/6/8
The following parameters represent design guaranteed performance.
Duty
45
50
55
%
Measured at a voltage of 1/2 of VDD
Period-Jitter 1σ
PJsSD
-
50
-
psec
1
Period-Jitter MIN-MAX
PJsABS
-
300
-
psec
2
Rise time
tr
-
2.5
-
nsec
Period of transition time required for the
output to reach 80% from 20% of VDD.
Provided with 15pF output load.
Fall time
tf
-
2.5
-
nsec
Period of transition time required for the
output to reach 20% from 80% of VDD.
Provided with 15pF output load.
Output Lock time
tLOCK
-
200
sec
3
Note) The output frequency is determined by the arithmetic (frequency division) expression of a frequency input to IN.
If the input frequency is set to 27.0000MHz, the output frequency will be as listed above.
BU7325HFV(Ta=25℃, VDD=3.3V, Crystal frequency=27.0000MHz, unless otherwise specified.)
Parameter
Symbol
Limits
Unit
Conditions
Min.
Typ.
Max.
Output H voltage
VOH
2.8
-
V
IOH=-4.0mA
Output L voltage
VOL
-
0.5
V
IOL=4.0mA
Pull-down resistance
Rpd
25
50
100
k
Pull-down resistance on input pin
Consumption current 1
IDD1
-
11
15
mA
OE=H, SEL=L, at no load
Consumption current 2
IDD2
-
12
16.5
mA
OE=H, SEL=H, at no load
Standby current
IDDst
-
1
A
OE=L
Output frequency
CLK_48
-
48.0000
-
MHz
SEL=L, IN*96/9/6
CLK_78
-
78.0000
-
MHz
SEL=H, IN*104/9/4
The following parameters represent design guaranteed performance.
Duty
45
50
55
%
Measured at a voltage of 1/2 of VDD
Period-Jitter 1σ
PJsSD
-
50
-
psec
1
Period-Jitter MIN-MAX
PJsABS
-
300
-
psec
2
Rise time
tr
-
1.5
-
nsec
Period of transition time required for the
output to reach 80% from 20% of VDD.
Provided with 15pF output load.
Fall time
tf
-
1.5
-
nsec
Period of transition time required for the
output to reach 20% from 80% of VDD.
Provided with 15pF output load.
Output Lock time
tLOCK
-
200
sec
3
Note) The output frequency is determined by the arithmetic (frequency division) expression of a frequency input to IN.
If the input frequency is set to 27.0000MHz, the output frequency will be as listed above.
Common to BU3071HFV, BU3072HFV, BU3073HFV, BU3076HFV, BU7322HFV, BU7325HFV
1
Period-Jitter 1σ
This parameter represents standard deviation (=1σ) on cycle distribution data at the time when the output clock cycles are sampled 1000 times
consecutively with the TDS7104 Digital Phosphor Oscilloscope of Tektronix Japan, Ltd.
2
Period-Jitter MIN-MAX
This parameter represents a maximum distribution width on cycle distribution data at the time when the output clock cycles are sampled 1000 times
consecutively with the TDS7104 Digital Phosphor Oscilloscope of Tektronix Japan, Ltd.
3
Output Lock Time
This parameter represents elapsed time after power supply turns ON to reach a voltage of 3.0 V, after the system is switched from Power-Down state to
normal operation state, or after the output frequency is switched, until it is stabilized at a specified frequency, respectively.
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