参数资料
型号: CS5464-ISZR
厂商: Cirrus Logic Inc
文件页数: 11/46页
文件大小: 0K
描述: IC ENERGY METERING 1PHASE 28SSOP
标准包装: 1,000
输入阻抗: 30 千欧
测量误差: 0.1%
电压 - 高输入/输出: 0.8V
电压 - 低输入/输出: 0.2V
电流 - 电源: 3.5mA
电源电压: 4.75 V ~ 5.25 V
测量仪表类型: 单相
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 28-SSOP(0.209",5.30mm 宽)
供应商设备封装: 28-SSOP
包装: 带卷 (TR)
配用: 598-1554-ND - BOARD EVAL FOR CS5464 ADC
CS5464
SWITCHING CHARACTERISTICS
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Min / Max characteristics and specifications are guaranteed over all Recommended Operating Conditions .
Typical characteristics and specifications are measured at nominal supply voltages and TA = 25 °C.
VA+ = 5 V ±5% VD+ = 3.3 V ±5% or 5 V ±5%; AGND = DGND = 0 V. All voltages with respect to 0 V.
Logic Levels: Logic 0 = 0 V, Logic 1 = VD+.
Rise Times
(Note 17)
Fall Times
(Note 17)
Parameter
Any Digital Output
Any Digital Output
Symbol
t rise
t fall
Min
-
-
-
-
Typ
-
50
-
50
Max
1.0
-
1.0
-
Unit
μs
ns
μs
ns
Start-up
Oscillator Start-up Time
XTAL = 4.096 MHz (Note 11)
t ost
-
60
-
ms
Serial Port Timing
Serial Clock Frequency
SCLK
-
-
2
MHz
Serial Clock
Pulse Width High
Pulse Width Low
t 1
t 2
200
200
-
-
-
-
ns
ns
SDI Timing
CS Falling to SCLK Rising
Data Set-up Time Prior to SCLK Rising
Data Hold Time After SCLK Rising
t 3
t 4
t 5
50
50
100
-
-
-
-
-
-
ns
ns
ns
SDO Timing
CS Falling to SDO Driving
SCLK Falling to New Data Bit (hold time)
CS Rising to SDO Hi-Z
t 6
t 7
t 8
-
-
-
20
20
20
50
50
50
ns
ns
ns
E 2 PROM mode Timing
Serial Clock
Pulse Width Low
t 9
8
DCLK
MODE setup time to RESET Rising
RESET rising to CS falling
Pulse Width High
t 10
t 11
t 12
50
48
8
DCLK
ns
DCLK
CS falling to SCLK rising
t 13
100
8
DCLK
SCLK falling to CS rising
CS rising to driving MODE low
SDO setup time to SCLK rising
t 14
t 15
t 16
50
100
16
DCLK
ns
ns
Notes: 17. Specified using 10% and 90% points on waveform of interest. Output loaded with 50 pF.
18. Oscillator start-up time varies with crystal parameters. This specification does not apply when using an
external clock source.
DS682F3
11
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