参数资料
型号: CS5509-ASZ
厂商: Cirrus Logic Inc
文件页数: 22/24页
文件大小: 0K
描述: IC ADC 16BIT SGNL SUPP 16-SOIC
标准包装: 47
位数: 16
采样率(每秒): 200
数据接口: 串行
转换器数目: 1
功率耗散(最大): 2.25mW
电压电源: 模拟和数字
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 16-SOIC(0.295",7.50mm 宽)
供应商设备封装: 16-SOIC
包装: 管件
输入数目和类型: 1 个差分,单极;1 个差分,双极
产品目录页面: 755 (CN2011-ZH PDF)
其它名称: 598-1100-5
CS5509
DS125F3
7
Notes: 16. If CS is activated asynchronously to DRDY, CS will not be recognized if it occurs when DRDY is high
for 2 clock cycles. The propagation delay time may be as great as 2 fclk cycles plus 200 ns. To guarantee
proper clocking of SDATA when using asynchronous CS, SCLK(i) should not be taken high sooner than
2 fclk + 200 ns after CS goes low.
17. SDATA transitions on the falling edge of SCLK. Note that a rising SCLK must occur to enable the serial
port shifting mechanism before falling edges can be recognized.
18. If CS is returned high before all data bits are output, the SDATA output will complete the current data
bit and then go to high impedance.
5V SWITCHING CHARACTERISTICS (T
A = 25 °C; VA+, VD+ = 5V ±5%; Input Levels: Logic 0 =
0V, Logic 1 = VD+; CL = 50 pF) (Note 2)
Parameter
Symbol
Min
Typ
Max
Unit
Serial Clock
fsclk
0-
2.5
MHz
Serial Clock
Pulse Width High
Pulse Width Low
tph
tpl
200
-
ns
Access Time
CS Low to data valid (Note 16)
tcsd
-60
200
ns
Maximum Delay Time
(Note 17)
SCLK falling to new SDATA bit
tdd
-150
310
ns
Output Float Delay
CS High to output Hi-Z (Note 18)
SCLK falling to Hi-Z
tfd1
tfd2
-
60
160
150
300
ns
3.3V SWITCHING CHARACTERISTICS (T
A = 25 °C; VA+ = 5V ±5%; VD+ = 3.3V ±5%; Input
Levels: Logic 0 = 0V, Logic 1 = VD+; CL = 50 pF) (Note 2)
Parameter
Symbol
Min
Typ
Max
Unit
Serial Clock
fsclk
0
-
1.25
MHz
Serial Clock
Pulse Width High
Pulse Width Low
tph
tpl
200
-
ns
Access Time
CS Low to data valid (Note 16)
tcsd
-100
200
ns
Maximum Delay Time
(Note 17)
SCLK falling to new SDATA bit
tdd
-400
600
ns
Output Float Delay
CS High to output Hi-Z (Note 18)
SCLK falling to Hi-Z
tfd1
tfd2
-
70
320
150
500
ns
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