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参数资料
| 型号： | CS5522-ASZR |
| 厂商： | Cirrus Logic Inc |
| 文件页数： | 33/56页 |
| 文件大小： | 0K |
| 描述： | IC ADC 24BIT 2CH 20-SSOP |
| 标准包装： | 1,000 |
| 位数： | 24 |
| 数据接口： | 串行 |
| 转换器数目： | 1 |
| 功率耗散（最大）： | 14.8mW |
| 电压电源： | 模拟和数字 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 20-SSOP（0.209"，5.30mm 宽） |
| 供应商设备封装： | 20-SSOP |
| 包装： | 带卷 (TR) |
| 输入数目和类型： | 2 个差分，单极；2 个差分，双极 |
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CS5521/22/23/24/28
DS317F8
39
SD0. After ‘1111 1111’ is provided, 24 additional
SCLKs are required to transfer the last 3 bytes of
conversion data before the serial port will return to
the command mode.
Example 3:
The configuration register has the following bits as
shown:
DP3-DP = ‘0101’,
MC = 1,
LP = 0,
RC = X. The command issued is ‘1XXX X000’.
These settings instruct the converter to perform a
single conversion on six Setups once. The order in
which the channels are converted is 6, 1, 6, 2, 6, and
3. SDO falls after physical channel 3 is converted.
To read the 6 conversion results 8 SCLKs are re-
quired to clear the SD0 flag. Then 144 additional
SCLKs are required to read the conversion data
from the FIFO. Again, the order in which the data
is provided is the same as the order in which the
channels are converted. After the last 3 bytes of the
conversion data corresponding to physical channel
3 is read, the serial port automatically returns to the
command mode where it will remain until the next
valid command byte is received.
Example 4:
The configuration register has the following bits as
shown:
DP3-DP0 = ‘1001’,
MC = 1,
LP = 1,
RC = 0.
The
command
byte
issued
is
‘1XXX X000’. These settings instruct the convert-
er to repeatedly perform multiple-setup conver-
sions using ten Setups. The order in which the
channels are converted is: 6, 1, 6, 2, 6, 3, 6, 4, 6, 5.
SDO falls after physical channel 5 is converted. To
read the 10 conversion results 8 SCLKs with
SDI = 0 are required to clear the SD0 flag. Then
240 more SCLKs are required to read the conver-
sion data from the FIFO. The order in which the
data is provided is the same as the order in which
the channels are converted. The first 3 bytes of data
correspond to the first Setup which in this example
is physical channel 6; the next 3 bytes of data cor-
respond to the second Setup which in this example
is physical channel 1; and, the last 3 bytes of data
corresponds to 10th Setup which here is physical
channel 5. Since the Setups are converted in the
background, while the data is being read, the user
must finish reading the conversion data FIFO be-
fore it is updated with new conversions. To exit this
conversion
mode
the
user
must
provide
‘1111 1111’ to SDI during the first 8 SCLKs. If a
byte of 1’s is provided, the serial port returns to the
command mode only after the conversion data
FIFO is emptied (in this case 10 conversions are
performed). Note that in this example physical
channel 6 is converted five times. Each conversion
could be with the same or different filter rates de-
pending on the setting of Setups 1, 3, 5, 7 and 9.
Note that there is only one offset and one gain reg-
ister per physical channel. Therefore, any physical
channel can only be calibrated for the gain range
selected during calibration. Specifying a different
gain range in the Setup other than the range that
was calibrated will result in a gain error.
Example 5:
The configuration register has the following bits as
shown: DP3-DP0 = ‘XXXX’, MC = X, LP = X,
RC = X. The command issued is ‘1010 1101’.
These settings instruct the converter to perform a
system offset calibration of the 6th Setup (which is
physical channel 3 in this example). During cali-
bration, the serial port remains in the command
mode. Once the calibration is completed, SDO
falls. To perform additional calibrations, more
commands have to be issued.
Notes: 1)The configuration register must be written before
channel-setup registers (CSRs) because the depth
information contained in the configuration regis-
ter defines how many of the CSRs to use.
2) The CSRs need to be written regardless of single
conversion or multiple single conversion mode.
3) When single-Setup conversions (MC = 0) are de-
sired, the channel address is embedded in the
command byte. In the multiple-Setup conversion
mode (MC = 1), channels are selected in a pre-
programmed order based on information con-
tained in the CSRs and the depth bits (DP3-DP0)
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相关代理商/技术参数 |
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| CS5523 | 制造商:CIRRUS 制造商全称:Cirrus Logic 功能描述:16-bit or 24-bit, 2/4/8-channel ADCs with PGIA |
| CS5523-AP | 制造商:CIRRUS 制造商全称:Cirrus Logic 功能描述:16 BIT OR 24 BIT 2/4/8 CHANNEL ADCS WITH PGIA |
| CS5523-AS | 功能描述:模数转换器 - ADC 4-Ch 16-Bit Delta Sigma ADC RoHS:否 制造商:Texas Instruments 通道数量:2 结构:Sigma-Delta 转换速率:125 SPs to 8 KSPs 分辨率:24 bit 输入类型:Differential 信噪比:107 dB 接口类型:SPI 工作电源电压:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:VQFN-32 |
| CS5523-ASZ | 功能描述:模数转换器 - ADC 4-Ch 16-Bit Delta Sigma ADC RoHS:否 制造商:Texas Instruments 通道数量:2 结构:Sigma-Delta 转换速率:125 SPs to 8 KSPs 分辨率:24 bit 输入类型:Differential 信噪比:107 dB 接口类型:SPI 工作电源电压:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:VQFN-32 |
| CS5523-ASZR | 功能描述:模数转换器 - ADC IC 2-Chl 16Bit Bffrd Dlt Sgm Mlt-Rng ADC RoHS:否 制造商:Texas Instruments 通道数量:2 结构:Sigma-Delta 转换速率:125 SPs to 8 KSPs 分辨率:24 bit 输入类型:Differential 信噪比:107 dB 接口类型:SPI 工作电源电压:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:VQFN-32 |
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