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参数资料
| 型号： | CS8414 |
| 厂商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 96 KHZ DIGITAL AUDIO RECEIVER |
| 中文描述： | 96 kHz的数字音频接收器 |
| 文件页数： | 7/38页 |
| 文件大小： | 646K |
| 代理商： | CS8414 |
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CS8413 CS8414
DS240F1
15
in the fourth and fifth special modes, the data is de-
layed only a few bit periods before being output.
However, error codes, and the C, U and V bits fol-
low the normal pathway with a two frame delay (so
that the error code would be output with the offend-
ing data in the other modes). As a result, in special
modes four and five, the error codes are nearly two
frames behind the data output on SDATA.
Buffer Memory
In all buffer modes, the status, mask, and control
registers are located at addresses 0-3, and the user
data is buffered at locations 4 through 7. The paral-
lel port can access any location in the user data
buffer at any time; however, care should be taken
not to read a location when that location is being
updated internally. This internal writing is done
through a second port of the buffer and is done in a
cyclic manner. As data is received, the bits are as-
sembled in an internal 8-bit shift register which,
when full, is loaded into the buffer memory. The
first bit received is stored in D0 and, after D7 is re-
ceived, the byte is written into the proper buffer
memory location.
The user data is received one bit per sub-frame. At
the channel status block boundary, the internal
pointer for writing user data is initialized to 04H
(Hex). After receiving eight user bits, the byte is
written to the address indicated by the user pointer
which is then incremented to point to the next ad-
dress. After receiving all four bytes of user data, 32
audio samples, the user pointer is set to 04H again
and the cycle repeats. FLAG0, in SR1 can be used
to monitor the user data buffer. When the last byte
of the user buffer, location 07H, is written, FLAG0
is set low and when the second byte, location 05H,
is written, FLAG0 is set high. If the corresponding
bit in the interrupt enable register (IER1, bit 0) is
set, a transition of FLAG0 will generate a low pulse
on the interrupt pin. The level of FLAG0 indicates
which two bytes the part will write next, thereby in-
dicating which two bytes are free to be read.
FLAG1 is buffer mode dependent and is discussed
in the individual buffer mode sections. A transition
of FLAG1 will generate an interrupt if the appro-
priate interrupt enable bit is set.
FLAG2 is set high after channel status byte 23, the
last byte of the block, is written and set low after
channel status byte 3 is written to the buffer mem-
ory. FLAG2 is unique in that only the rising edge
can cause an interrupt if the appropriate interrupt
enable bit in IER1 is set.
Figure 11 illustrates the flag timing for an entire
channel status block which includes 24 bytes of
channel status data per channel and 384 audio sam-
ples. The lower portion of Figure 11 expands the
first byte of channel status showing eight pairs of
data, with a pair defined as a frame. This is further
expanded showing the first sub-frame (A0) to con-
tain 32 bits defined as per the digital audio stan-
dards. When receiving stereo, channel A is left and
channel B is right.
For all three buffer modes, the three most signifi-
cant bits in SR1, shown in Figure 6, can be used to
monitor the channel status data. In buffer mode 2,
bits 7 and 6 change definition and are described in
that section. Channel status data, as described in the
standards, is independent for each channel. Each
channel contains its own block of channel status
data, and in most systems, both channels will con-
tain the same channel status data. Buffer modes 0
and 1 operate on one block of channel status with
the particular block selected by the CS2/CS1 bit in
CR1. CSDIF, bit 7 in SR1, indicates when the
channel status data for each channel is not the same
even though only one channel is being buffered.
CRCE, bit 6 in SR1, indicates a CRC error oc-
curred in the buffered channel. CCHG, bit 5 in
SR1, is set when any bit in the buffered channel sta-
tus bytes 0 to 3, change from one block to the next.
相关PDF资料 |
PDF描述 |
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| CS8414-CS | 96 KHZ DIGITAL AUDIO RECEIVER |
| CSB7152-01 | 70 V, SILICON, PIN DIODE |
| CSBFB1M00J58-R1 | CERAMIC RESONATOR, 1 MHz |
| CSBLA400KECE-B0 | CERAMIC RESONATOR, 0.4 MHz |
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相关代理商/技术参数 |
参数描述 |
|---|---|
| CS8414CS | 制造商:CRYS 功能描述: 制造商:The Cherry Corporation 功能描述: |
| CS8414-CS | 制造商:Rochester Electronics LLC 功能描述: 制造商:Cirrus Logic 功能描述: |
| CS8414-CSR | 制造商:Rochester Electronics LLC 功能描述: 制造商:Cirrus Logic 功能描述: |
| CS8414-CSZ | 功能描述:音频 DSP IC 96 kHz Digital Audio Receivers RoHS:否 制造商:Texas Instruments 工作电源电压: 电源电流: 工作温度范围: 安装风格: 封装 / 箱体: 封装:Tube |
| CS8414-CSZ/A | 制造商:Cirrus Logic 功能描述: |
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