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参数资料
| 型号： | CX74038-71 |
| 厂商： | SKYWORKS SOLUTIONS INC |
| 元件分类： | PLL合成/DDS/VCOs |
| 英文描述： | PLL FREQUENCY SYNTHESIZER, 2600 MHz, CQCC24 |
| 封装： | 4.50 X 3.50 MM, 1 MM HEIGHT, CSP-24 |
| 文件页数： | 11/17页 |
| 文件大小： | 988K |
| 代理商： | CX74038-71 |
Data Sheet I CX74038
Technical Description
A dithering disable function is accessible via word 00, data bits
21 and 20. When the RF synthesizer is programmed for
fractional divide values, these bits should be programmed to 1
0 (dithering enable). However, when the RF synthesizer is
programmed to output a frequency which is a whole integer
multiple of the comparison frequency, the synthesizer should
be programmed for dithering disabled (bits set to 11). This
improves the phase noise when operating on integer-N
boundaries. These data bits must be programmed after power-
up, otherwise erroneous device operation may occur. Refer to
the Synthesizer Register Programming section of this
document for bit definitions.
The CX74038 has two package options: the 20-pin TSSOP and
the 24-pin 3.5 x 4.5 mm CSP. The device pinouts are shown in
Figures 1 and 2, respectively.
The CX74038 is a fractional-N frequency synthesizer using a
Σ modulation technique. The fractional-N implementation
provides low in-band noise by having a low division ratio and
fast frequency settling time. In addition, the CX74038 provides
arbitrarily fine frequency resolution with a digital word, so that
the frequency synthesizer can be used to compensate for
crystal frequency drift in the RF transceiver.
Voltage Controlled Oscillator (VCO) Prescalers
Σ Modulator
The VCO prescalers, P/P+1 and Q/Q+1, provide low noise
signal conditioning of the VCO signals. They translate from an
off-chip, single-ended or differential signal to an on-chip
differential signal. By changing the PS bit, the RF synthesizer
has the option to use either the 8/9 or the 16/17 prescaler
depending on the desired operational frequency. The
maximum frequency is 2.6 GHz and 2.0 GHz for the 16/17 and
8/9 prescalers, respectively. The IF synthesizer has a fixed
16/17 prescaler with a maximum frequency of 800 MHz.
The primary limitation of conventional fractional-N synthesizers
is the fractional spurs. The CX74038
Σ technique improves
the synthesizer performance by randomizing the spurs using
internal dithering.
Serial Interface
The serial interface is a versatile three-wire interface
consisting of three pins: serial clock (CLK), serial input (DAT),
and Latch Enable (LE). It enables the CX74038 to operate in a
system where one or multiple masters and slaves are present.
For more information, refer to the Synthesizer Register
Programming section of this document.
RF and IF Dividers
The CX74038 provides programmable dividers that control the
prescaler and supply the divided VCO signals to the charge
pump phase detectors. Programmable ratios on the RF
fractional-N synthesizer ranging from 256 to 212 are possible
with the 16/17 prescaler, and from 64 to 211 with the 8/9
prescaler. The IF integer-N synthesizer has a programmable
divide ratio ranging from 256 to 217.
LE is set low before the rising edge of the 1st clock (CLK) pulse
and is held low until after the last (22nd) clock pulse, at which
time LE is set high. The data word is transferred to the correct
device register when LE is high (there are four internal
registers selected by the D1 and D0 bits of the 22-bit
data/address word). If the LE signal does not go high, the data
does not get transferred to the register. Between each 22-bit
data/address word transfer, LE must be pulsed to make the
transfer to the specific device register. Data/address transfer is
MSB first.
Reference Frequency Dividers
The reference signal can be divided by a ratio of 1 to 7 for the
RF reference divider (R1) and from 1 to 8192 for the IF
reference divider (R2). The input frequency for the reference
signal can be as high as 50 MHz.
LE must not go high when CLK is high; otherwise, the data
word is not transferred to the register. LE must only go high
after CLK has gone low.
Phase Detectors and Charge Pumps
The CX74038 uses a separate charge pump phase detector for
each synthesizer. The IF and RF Phase/Frequency Detector
(PFD) can have a programmable charge pump current from 0.4
mA to 1.6 mA and 120
A to 480 A, respectively.
After the transfer of the last 22-bit data/address word, the LE
signal can be left in a high state. It does not have to be
returned to a low state unless another data/address word
transfer is required.
For optimum performance, the divided reference frequency
presented at the phase detector input must not exceed 9 MHz
using the RF 16/17 prescaler synthesizer mode, 15 MHz using
the RF 8/9 prescaler, or 2 MHz for the IF synthesizer mode.
The comparison frequency is also limited by the desired
frequency divided by the minimum divide ratio.
It is not necessary to write all four data/address words to the
synthesizer to make a change in programming. For example, if
a change to the Lock Detect (LD) pin operation is desired, only
word 00 has to be changed.
Registers
The charge-pump can be programmed to high impedance (Hi-
Z) state for open-loop VCO modulation use.
The CX74038 includes four 22-bit registers that can be
programmed independently in any order. Bits D0 and D1
represent the register addresses. For more information on
registers, addresses, and format, refer to the Synthesizer
Register Programming section of this document.
Lock Detection
The output of the IF/RF dividers (R1, N1, R2, N2) and lock
detectors for both synthesizers can be multiplexed to the LD
pin. When programmed for lock detection, the CX74038
Skyworks Solutions, Inc., Proprietary and Confidential
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101075F
[781] 376-3000 I FAX [781] 376-3100 I SALES@SKYWORKSINC.COM I WWW.SKYWORKSINC.COM
MARCH 7, 2003
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