参数资料
型号: CY2040-3
厂商: Cypress Semiconductor Corp.
英文描述: 32 kHz and 24 MHz Clock Generator with Precision 32 kHz Input
中文描述: 32 kHz和24兆赫的精密时钟发生器,32 kHz输入
文件页数: 6/7页
文件大小: 67K
代理商: CY2040-3
CY2040-2/3
Document #: 38-07122 Rev. *A
Page 6 of 7
Cypress Semiconductor Corporation, 2001. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
Application Circuits
All product and company names mentioned in this document are the trademarks of their respective holders.
Ordering Code
Package Name
Package Type
Operating Range
CY2040ZC-2
Z16
16LD TSSOP
0
70
°
C
CY2040ZC-3
Z16
16LD TSSOP
0
70
°
C
CY2040-3
1 NC
2 32KPLLEN
3 PD24M#
4 V32K
5 V24M
6 Xin32K
7 Xout32K
8 NC
Vss 16
out24M 15
Out32KPLL 14
Out32K 13
Xout24M 12
Xin24M 11
Vss 10
NC 9
Vdd
0.1uF
32.768KHz
Crystal
Note 2
GND
GND
24.000MHz
Crystal
CY2040-2
1 NC
2 32KPLLEN
3 PD24M#
4 V32K
5 V24M
6 Xin32K
7 Xout32K
8 NC
Vss 16
out24M 15
Out32KPLL 14
Out32K 13
Xout24M 12
Xin24M 11
Vss 10
NC 9
Vdd
0.1uF
32.000kHz
Crystal
Note 2
GND
GND
CY2040-3
CY2040-2
Note:
2.
To disable the OUT32KPLL output, the 32KPLLEN pin should be connected to GND. To enable the OUT32KPLL output, the 32KPLLEN pin should
be connected to V
DD
.
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