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参数资料
| 型号： | CY2213ZC-2 |
| 厂商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分类： | XO, clock |
| 英文描述： | High-Frequency Programmable PECL Clock Generator |
| 中文描述： | 500 MHz, OTHER CLOCK GENERATOR, PDSO16 |
| 封装： | 4.40 MM, TSSOP-16 |
| 文件页数： | 7/10页 |
| 文件大小： | 103K |
| 代理商： | CY2213ZC-2 |
CY2213
Document #: 38-07263 Rev. *E
Page 7 of 10
The PECL differential driver is designed for low-voltage,
high-frequency operation. It significantly reduces the transient
switching noise and power dissipation when compared to
conventional CMOS drivers. The nominal value of the channel
impedance is 50
. The pull-up and pull-down resistors provide
matching channel termination. The combination of the differ-
ential driver and the output network determines the voltage
swing on the channel. The output clock is specified at the
measurement point indicated in
Figure 5
and
Figure 6
.
Signal Waveforms
A physical signal that appears at the pins of the device is
deemed valid or invalid depending on its voltage and timing
relations with other signals. This section defines the voltage
and timing waveforms for the input and output pins of the
CY2213. The Device Characteristics tables list the specifica-
tions for the device parameters that are defined here.
Input and Output voltage waveforms are defined as shown in
Figure 8
. Rise and fall times are defined as the 20% and 80%
measurement points of V
OHmin
– V
OLmax
.
The device parameters are defined in
Table 1
.
Figure 9
shows
the definition of long-term duty cycle, which is simply the CLK
waveform high-time divided by the cycle time (defined at the
crossing point). Long-term duty cycle is the average over
many (> 10,000) cycles. DC is defined as the output clock
long-term duty cycle.
Jitter
This section defines the specifications that relate to timing
uncertainty (or jitter) of the input and output waveforms.
Figure 10
shows the definition of period jitter with respect to
the falling edge of the CLK signal. Period jitter is the difference
between the minimum and maximum cycle times over many
cycles (typically 12800 cycles at 400 MHz). Equal require-
ments apply for rising edges of the CLK signal. t
JP
is defined
as the output period jitter.
Figure 11
shows the definition of cycle-to-cycle jitter with
respect to the falling edge of the CLK signal. Cycle-to-cycle
jitter is the difference between cycle times of adjacent cycles
over many cycles (typically 12800 cycles at 400 MHz). Equal
requirements apply for rising edges of the CLK signal. t
JC
is
defined as the clock output cycle-to-cycle jitter.
Table 1. Definition of Device Parameters
Parameter
V
OH
, V
OL
V
IH
, V
IL
t
CR
, t
CF
Definition
Clock output high and low voltages
V
DD
LVCMOS input high and low voltages
Clock output rise and fall times
t
CR
t
CF
V(t)
V
OHmin
80%
20%
V
OLmax
Figure 8. Voltage Waveforms
t
PW+
t
CYCLE
CLK
CLKB
DC = t
PW+
/t
CYCLE
Figure 9. Duty CycleJitter
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相关代理商/技术参数 |
参数描述 |
|---|---|
| CY2213ZC-2T | 制造商:CYPRESS 制造商全称:Cypress Semiconductor 功能描述:High-Frequency Programmable PECL Clock Generator |
| CY2213ZXC-1 | 功能描述:锁相环 - PLL HI FREQUENCY PRGMBLE PECL CLOCK GEN RoHS:否 制造商:Silicon Labs 类型:PLL Clock Multiplier 电路数量:1 最大输入频率:710 MHz 最小输入频率:0.002 MHz 输出频率范围:0.002 MHz to 808 MHz 电源电压-最大:3.63 V 电源电压-最小:1.71 V 最大工作温度:+ 85 C 最小工作温度:- 40 C 封装 / 箱体:QFN-36 封装:Tray |
| CY2213ZXC-1KN | 制造商:Rochester Electronics LLC 功能描述: 制造商:Cypress Semiconductor 功能描述: |
| CY2213ZXC-1T | 功能描述:锁相环 - PLL HI FREQUENCY PRGMBLE PECL CLOCK GEN RoHS:否 制造商:Silicon Labs 类型:PLL Clock Multiplier 电路数量:1 最大输入频率:710 MHz 最小输入频率:0.002 MHz 输出频率范围:0.002 MHz to 808 MHz 电源电压-最大:3.63 V 电源电压-最小:1.71 V 最大工作温度:+ 85 C 最小工作温度:- 40 C 封装 / 箱体:QFN-36 封装:Tray |
| CY2213ZXC-2 | 功能描述:锁相环 - PLL HI Freq PECL Clock Generator RoHS:否 制造商:Silicon Labs 类型:PLL Clock Multiplier 电路数量:1 最大输入频率:710 MHz 最小输入频率:0.002 MHz 输出频率范围:0.002 MHz to 808 MHz 电源电压-最大:3.63 V 电源电压-最小:1.71 V 最大工作温度:+ 85 C 最小工作温度:- 40 C 封装 / 箱体:QFN-36 封装:Tray |
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