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参数资料
| 型号： | CY22150FC |
| 厂商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分类： | XO, clock |
| 英文描述： | One-PLL General-Purpose Flash-Programmable and 2-Wire Serially Programmable Clock Generator |
| 中文描述： | 200 MHz, OTHER CLOCK GENERATOR, PDSO16 |
| 封装： | 4.40 MM, MO-153, TSSOP-16 |
| 文件页数： | 6/13页 |
| 文件大小： | 211K |
| 代理商： | CY22150FC |
CY22150
Document #: 38-07104 Rev. *F
Page 6 of 13
Although using the above table will guarantee stability, it is
recommended to use the Print Preview function in
CyClocksRT to determine the correct charge pump settings for
optimal jitter performance.
PLL stability cannot be guaranteed for values below 16 and
above 1023. If values above 1023 are needed, use
CyClocksRT to determine the best charge pump setting.
Clock Output Settings: CLKSRC – Clock Output Cross-
point Switch Matrix [44H(7..0)], [45H(7..0)], [46H(7..6)]
CLKOE – Clock Output Enable Control [09H(5..0)]
Every clock output can be defined to come from one of seven
unique frequency sources. The CLKSRC(2..0) crosspoint
switch matrix defines which source is attached to each
individual clock output. CLKSRC(2..0) is set in Registers 44H,
45H, and 46H. The remainder of register 46H(5:0) must be
written with the values stated in the register table when writing
register values 46H(7:6).
In addition, each clock output has individual CLKOE control,
set by register 09H(5..0).
When DIV1N is divisible by four, then CLKSRC(0,1,0) is
guaranteed
to
be
rising
CLKSRC(0,0,1). When DIV1N is six, then CLKSRC(0,1,1) is
edge
phase-aligned
with
guaranteed
CLKSRC(0,0,1).
When DIV2N is divisible by four, then CLKSRC(1,0,1) is
guaranteed
to
be
rising
CLKSRC(1,0,0). When DIV2N is divisible by eight, then
CLKSRC(1,1,0) is guaranteed to be rising edge phase-aligned
with CLKSRC(1,0,0).
Each clock output has its own output enable, controlled by
register 09H(5..0). To enable an output, set the corresponding
CLKOE bit to 1. CLKOE settings are in
Table 13
.
The output swing of LCLK1 through LCLK4 is set by V
DDL
. The
output swing of CLK5 and CLK6 is set by V
DD
.
to
be
rising
edge
phase-aligned
with
edge
phase-aligned
with
Test, Reserved, and Blank Registers
Writing to any of the following registers will cause the part to
exhibit abnormal behavior, as follows.
[00H to 08H]
– Reserved
[0AH to 0BH]
– Reserved
[0DH to 11H]
– Reserved
[14H to 3FH]
– Reserved
[43H]
– Reserved
[48H to FFH]
– Reserved.
Table 6. P Counter Register Definition
Address
40H
41H
42H
D7
1
D6
1
D5
0
D4
D3
D2
D1
D0
Pump(2)
PB(4)
Q(4)
Pump(1)
PB(3)
Q(3)
Pump(0)
PB(2)
Q(2)
PB(9)
PB(1)
Q(1)
PB(8)
PB(0)
Q(0)
PB(7)
PO
PB(6)
Q(6)
PB(5)
Q(5)
Table 7. P Counter Register Definition
Address
40H
41H
42H
D7
1
D6
1
D5
0
D4
D3
D2
D1
D0
Pump(2)
PB(4)
Q(4)
Pump(1)
PB(3)
Q(3)
Pump(0)
PB(2)
Q(2)
PB(9)
PB(1)
Q(1)
PB(8)
PB(0)
Q(0)
PB(7)
PO
PB(6)
Q(6)
PB(5)
Q(5)
Table 8. PLL Post Divider Options
Address
OCH
47H
D7
D6
D5
D4
D3
D2
D1
D0
DIV1SRC
DIV2SRC
DIV1N(6)
DIV2N(6)
DIV1N(5)
DIV2N(5)
DIV1N(4)
DIV2N(4)
DIV1N(3)
DIV2N(3)
DIV1N(2)
DIV2N(2)
DIV1N(1)
DIV2N(1)
DIV1N(0)
DIV2N(0)
Table 9. Charge Pump Settings
Charge Pump Setting – Pump(2..0)
000
001
010
011
100
101, 110, 111
Calculated P
total
16 – 44
45 – 479
480 – 639
640 – 799
800 – 1023
Do not use – device will be unstable
Table 10. Register 40H Change Pump Bit Settings
Address
40H
D7
1
D6
1
D5
0
D4
D3
D2
D1
PB(9)
D0
PB(8)
Pump(2)
Pump(1)
Pump(0)
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相关代理商/技术参数 |
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| CY22150FCT | 制造商:Cypress Semiconductor 功能描述: |
| CY22150FI | 制造商:CYPRESS 制造商全称:Cypress Semiconductor 功能描述:One-PLL General-Purpose Flash-Programmable and 2-Wire Serially Programmable Clock Generator |
| CY22150FZXC | 功能描述:锁相环 - PLL 1-PLL Clk Syn COM RoHS:否 制造商:Silicon Labs 类型:PLL Clock Multiplier 电路数量:1 最大输入频率:710 MHz 最小输入频率:0.002 MHz 输出频率范围:0.002 MHz to 808 MHz 电源电压-最大:3.63 V 电源电压-最小:1.71 V 最大工作温度:+ 85 C 最小工作温度:- 40 C 封装 / 箱体:QFN-36 封装:Tray |
| CY22150FZXCT | 功能描述:锁相环 - PLL 1-PLL Clk Syn COM RoHS:否 制造商:Silicon Labs 类型:PLL Clock Multiplier 电路数量:1 最大输入频率:710 MHz 最小输入频率:0.002 MHz 输出频率范围:0.002 MHz to 808 MHz 电源电压-最大:3.63 V 电源电压-最小:1.71 V 最大工作温度:+ 85 C 最小工作温度:- 40 C 封装 / 箱体:QFN-36 封装:Tray |
| CY22150FZXI | 功能描述:锁相环 - PLL 1-PLL Clk Syn IND RoHS:否 制造商:Silicon Labs 类型:PLL Clock Multiplier 电路数量:1 最大输入频率:710 MHz 最小输入频率:0.002 MHz 输出频率范围:0.002 MHz to 808 MHz 电源电压-最大:3.63 V 电源电压-最小:1.71 V 最大工作温度:+ 85 C 最小工作温度:- 40 C 封装 / 箱体:QFN-36 封装:Tray |
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