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| 型号： | CY22150FI |
| 厂商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分类： | XO, clock |
| 英文描述： | One-PLL General-Purpose Flash-Programmable and 2-Wire Serially Programmable Clock Generator |
| 中文描述： | 166.6 MHz, OTHER CLOCK GENERATOR, PDSO16 |
| 封装： | 4.40 MM, MO-153, TSSOP-16 |
| 文件页数： | 4/13页 |
| 文件大小： | 211K |
| 代理商： | CY22150FI |
CY22150
Document #: 38-07104 Rev. *F
Page 4 of 13
manufacturer), and the CapLoad setting during crystal
start-up.
Bits 3 and 4 of register 12H control the input crystal oscillator
gain setting. Bit 4 is the MSB of the setting, and bit 3 is the
LSB. The setting is programmed according to
Table 2
. All other
bits in the register are reserved and should be programmed as
shown in
Table 3
.
Using an External Clock as the Reference Input
The CY22150 can also accept an external clock as reference,
with speeds up to 133 MHz. With an external clock, the XDRV
(register 12H) bits must be set according to
Table 4
.
Table 1. Summary Table – CY22150 Programmable Registers
Register
09H
OCH
Description
CLKOE control
DIV1SRC mux and
DIV1N divider
Input crystal oscillator
drive control
Input load capacitor
control
Charge Pump and PB
counter
D7
0
D6
0
D5
CLK6
DIV1N(5)
D4
CLK5
DIV1N(4)
D3
D2
D1
D0
LCLK4
DIV1N(3)
LCLK3
DIV1N(2)
LCLK2
DIV1N(1)
LCLK1
DIV1N(0)
DIV1SRC DIV1N(6)
12H
0
0
1
XDRV(1)
XDRV(0)
0
0
0
13H
CapLoad
(7)
1
PB(7)
PO
CapLoad
(6)
1
PB(6)
Q(6)
CapLoad
(5)
0
PB(5)
Q(5)
CapLoad
(4)
Pump(2)
PB(4)
Q(4)
CapLoad
(3)
Pump(1)
PB(3)
Q(3)
CapLoad
(2)
Pump(0)
PB(2)
Q(2)
CapLoad
(1)
PB(9)
PB(1)
Q(1)
CapLoad
(0)
PB(8)
PB(0)
Q(0)
40H
41H
42H
PO counter, Q
counter
Crosspoint switch
matrix control
44H
CLKSRC2
for LCLK1
CLKSRC0
for LCLK3
CLKSRC1
for CLK6
DIV2SRC DIV2N(6)
CLKSRC1
for LCLK1
CLKSRC2
for LCLK4
CLKSRC0
for CLK6
CLKSRC0
for LCLK1
CLKSRC1
for LCLK4
1
CLKSRC2
for LCLK2
CLKSRC0
for LCLK4
1
CLKSRC1
for LCLK2
CLKSRC2
for CLK5
1
CLKSRC0
for LCLK2
CLKSRC1
for CLK5
1
CLKSRC2
for LCLK3
CLKSRC0
for CLK5
1
CLKSRC1
for LCLK3
CLKSRC2
for CLK6
1
45H
46H
47H
DIV2SRC mux and
DIV2N divider
DIV2N(5)
DIV2N(4)
DIV2N(3)
DIV2N(2)
DIV2N(1)
DIV2N(0)
Table 2. Programmable Crystal Input Oscillator Gain Settings
Cap Register Settings
Effective Load Capacitance
(CapLoad)
Crystal ESR
8 – 15 MHz
15 – 20 MHz
20 – 25 MHz
25 – 30 MHz
00H – 80H
80H – C0H
C0H – FFH
6 pF to 12 pF
30
00
01
01
10
12pF to 18pF
30
01
01
10
10
18pF to 30pF
30
01
10
10
11
60
01
10
10
10
60
10
10
10
11
60
10
10
11
N/A
Crystal Input
Frequency
Table 3. Bit Locations and Values
Address
12H
D7
0
D6
0
D5
1
D4
D3
D2
0
D1
0
D0
0
XDRV(1)
XDRV(0)
Table 4. Programmable External Reference Input Oscillator Drive Settings
Reference Frequency
Drive Setting
1 – 25 MHz
00
25 – 50 MHz
01
50 – 90 MHz
10
90 – 133 MHz
11
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