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| 型号： | CY22392 |
| 厂商： | Cypress Semiconductor Corp. |
| 英文描述： | Three-PLL General Purpose FLASH Programmable Clock Generator(通用三锁相环FLASH可编程时钟发生器) |
| 中文描述： | 三锁相环通用闪存可编程时钟发生器（通用三锁相环闪存可编程时钟发生器） |
| 文件页数： | 5/8页 |
| 文件大小： | 175K |
| 代理商： | CY22392 |
CY22392
Document #: 38-07013 Rev. *D
Page 5 of 8
Electrical Characteristics
Parameter
Description
Conditions
Min.
Typ.
Max.
Unit
I
OH
I
OL
C
XTAL_MIN
C
XTAL_MAX
C
LOAD_IN
V
IH
V
IL
I
IH
I
IL
I
OZ
I
DD
Output High Current
[3]
Output Low Current
[3]
Crystal Load Capacitance
[3]
Crystal Load Capacitance
[3]
Input Pin Capacitance
[3]
V
OH
= V
DD
– 0.5, V
DD
= 3.3 V
V
OL
= 0.5V, V
DD
= 3.3 V
Capload at minimum setting
12
24
–
mA
12
24
–
mA
–
6
–
pF
Capload at maximum setting
–
30
–
pF
Except crystal pins
–
7
–
pF
HIGH-Level Input Voltage
CMOS levels,% of AV
DD
CMOS levels,% of AV
DD
V
IN
= AV
DD
– 0.3 V
V
IN
= +0.3 V
Three-state outputs
70%
–
–
AV
DD
AV
DD
μ
A
μ
A
μ
A
LOW-Level Input Voltage
–
–
30%
Input HIGH Current
–
<1
10
Input LOW Current
–
<1
10
Output Leakage Current
–
10
Total Power Supply Current
3.3V Power Supply; 2 outputs @
166 MHz; 4 outputs @ 83 MHz
–
100
–
mA
3.3V Power Supply; 2 outputs @
20 MHz; 4 outputs @ 40 MHz
–
50
–
mA
I
DDS
Total Power Supply Current in
Shutdown Mode
Shutdown active
–
5
20
μ
A
Switching Characteristics
Parameter
Name
Description
Min.
Typ.
Max.
Unit
1/t
1
Output Frequency
[3, 4]
Clock output limit, Commercial
–
–
200
MHz
Clock output limit, Industrial
Duty cycle for outputs, defined as t
2
÷
t
1
,
Fout < 100 MHz, divider >= 2, measured at V
DD
/2
Duty cycle for outputs, defined as t
2
÷
t
1
,
Fout > 100 MHz or divider = 1, measured at V
DD
/2
–
–
166
MHz
t
2
Output Duty Cycle
[3, 5]
45%
50%
55%
40%
50%
60%
t
3
t
4
Rising Edge Slew Rate
[3]
Output clock rise time, 20% to 80% of V
DD
Falling Edge Slew
Rate
[3]
0.75
1.4
–
V/ns
Output clock fall time, 20% to 80% of V
DD
0.75
1.4
–
V/ns
t
5
Output three-state
Timing
[3]
Clock Jitter
[3, 6]
Time for output to enter or leave three-state mode
after SHUTDOWN/OE switches
–
150
300
ns
t
6
Peak-to-peak period jitter, CLK outputs measured
at V
DD
/2
PLL Lock Time from Power-up
–
400
–
ps
t
7
Lock Time
[3]
–
1.0
3
ms
Notes:
3. Guaranteed by design, not 100% tested.
4. Guaranteed to meet 20%–80% output thresholds and duty cycle specifications.
5. Reference Output duty cycle depends on XTALIN duty cycle.
6. Jitter varies significantly with configuration. Reference Output jitter depends on XTALIN jitter and edge rate.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| CY22392_08 | 制造商:CYPRESS 制造商全称:Cypress Semiconductor 功能描述:Three-PLL General Purpose FLASH Programmable Clock Generator |
| CY22392_13 | 制造商:CYPRESS 制造商全称:Cypress Semiconductor 功能描述:Three-PLL General Purpose Flash Programmable Clock Generator |
| CY22392FC | 功能描述:IC CLKSYN FLSH PROG 3PLL 16TSSOP RoHS:否 类别:集成电路 (IC) >> 时钟/计时 - 时钟发生器，PLL，频率合成器 系列:- 产品变化通告:Product Discontinuation 04/May/2011 标准包装:96 系列:- 类型:时钟倍频器，零延迟缓冲器 PLL:带旁路 输入:LVTTL 输出:LVTTL 电路数:1 比率 - 输入:输出:1:8 差分 - 输入:输出:无/无 频率 - 最大:133.3MHz 除法器/乘法器:是/无 电源电压:3 V ~ 3.6 V 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:16-TSSOP（0.173"，4.40mm 宽） 供应商设备封装:16-TSSOP 包装:管件 其它名称:23S08-5HPGG |
| CY22392FCT | 制造商:Cypress Semiconductor 功能描述:Programmable PLL Clock Generator Triple 16-Pin TSSOP T/R |
| CY22392FI | 制造商:Cypress Semiconductor 功能描述: |
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