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参数资料
| 型号： | CY2273A-1 |
| 厂商： | Cypress Semiconductor Corp. |
| 英文描述： | Pentium㈢/II, 6x86, K6 Clock Synthesizer/Driver for Desktop PCs with Intel 82430TX, 82440LX or ALI IV/IV+, AGP and 3 DIMMs |
| 中文描述： | 奔腾㈢/ 2，6x86，K6时钟合成器/与英特尔82430TX，82440LX或阿里四/四，AGP和3个DIMM台式机驱动 |
| 文件页数： | 9/14页 |
| 文件大小： | 178K |
| 代理商： | CY2273A-1 |
CY2273A
9
Switching Characteristics for CY2273A-4
[8]
Over the Operating Range
Parameter
Output
Description
Test Conditions
Min.
Typ.
Max.
Unit
t
1
t
2
All
Output Duty Cycle
[9]
t
1
= t
1A
÷
t
1B
Between 0.4V and 2.0V, V
DDCPU
= 2.5V
45
50
55
%
CPUCLK
CPU Clock Rising and
Falling Edge Rate
0.75
1.0
4.0
V/ns
t
2
SDRAM
PCI, REF0,
USB
SDRAM, PCI, REF0,
USB Clock Rising and
Falling Edge Rate
Between 0.4V and 2.4V
0.85
1.0
4.0
V/ns
t
3
t
4
t
5
t
6
CPUCLK
CPU Clock Rise Time
Between 0.4V and 2.0V, V
DDCPU
= 2.5V
Between 2.0V and 0.4V, V
DDCPU
= 2.5V
Measured at 1.25V
0.4
2.13
ns
CPUCLK
CPU Clock Fall Time
0.4
2.13
ns
CPUCLK
CPU-CPU Clock Skew
100
250
ps
CPUCLK,
PCICLK
CPU-PCI Clock Skew
Measured at 1.25V for 2.5V clocks, and
at 1.5V for 3.3V clocks
1200
ps
t
7
CPUCLK,
SDRAM
CPU-SDRAM Clock
Skew
Measured at 1.25V for 2.5V clocks, and
at 1.5V for 3.3V clocks
650
ps
t
8
PCICLK,
PCICLK
PCI-PCI Clock Skew
Measured at 1.5V
500
ps
t
10
t
10
t
10
t
11
CPUCLK,
Cycle-Cycle Clock Jitter
Measured at 1.25V, V
DDCPU
= 2.5V
Measured at 1.5V
650
ps
SDRAM
Cycle-Cycle Clock Jitter
650
ps
PCICLK
Cycle-Cycle Clock Jitter
Measured at 1.5V
1200
ps
CPUCLK,
PCICLK,
SDRAM
Power-up Time
CPU, PCI, AGP, and SDRAM clock sta-
bilization from power-up
3
ms
Timing Requirement for the I
2
C Bus
Parameter
t
12
t
13
t
14
t
15
t
16
t
17
t
18
Description
Min.
0
4.7
4
4.7
4
4.7
Max.
100
Unit
kHz
μ
s
μ
s
μ
s
μ
s
μ
s
μ
s
SCLK Clock Frequency
Time the bus must be free before a new transmission can start
Hold time start condition. After this period the first clock pulse is generated.
The Low period of the clock.
The High period of the clock.
Set-up time for start condition. (Only relevant for a repeated start condition.)
Hold time DATA
for CBUS compatible masters.
for I
2
C devices
DATA input set-up time
Rise time of both SDATA and SCLK inputs
Fall time of both SDATA and SCLK inputs
Se-up time for stop condition
5
0
t
19
t
20
t
21
t
22
250
ns
μ
s
ns
μ
s
1
300
4.0
Switching Waveforms
Duty Cycle Timing
t
1A
t
1B
相关PDF资料 |
PDF描述 |
|---|---|
| CY2273A-2 | Pentium㈢/II, 6x86, K6 Clock Synthesizer/Driver for Desktop PCs with Intel 82430TX, 82440LX or ALI IV/IV+, AGP and 3 DIMMs |
| CY2273A-3 | Pentium㈢/II, 6x86, K6 Clock Synthesizer/Driver for Desktop PCs with Intel 82430TX, 82440LX or ALI IV/IV+, AGP and 3 DIMMs |
| CY2273A-4 | Pentium㈢/II, 6x86, K6 Clock Synthesizer/Driver for Desktop PCs with Intel 82430TX, 82440LX or ALI IV/IV+, AGP and 3 DIMMs |
| CY2273APVC-2 | Pentium㈢/II, 6x86, K6 Clock Synthesizer/Driver for Desktop PCs with Intel 82430TX, 82440LX or ALI IV/IV+, AGP and 3 DIMMs |
| CY2273APVC-3 | Pentium㈢/II, 6x86, K6 Clock Synthesizer/Driver for Desktop PCs with Intel 82430TX, 82440LX or ALI IV/IV+, AGP and 3 DIMMs |
相关代理商/技术参数 |
参数描述 |
|---|---|
| CY2273A-2 | 制造商:CYPRESS 制造商全称:Cypress Semiconductor 功能描述:Pentium㈢/II, 6x86, K6 Clock Synthesizer/Driver for Desktop PCs with Intel 82430TX, 82440LX or ALI IV/IV+, AGP and 3 DIMMs |
| CY2273A-3 | 制造商:CYPRESS 制造商全称:Cypress Semiconductor 功能描述:Pentium㈢/II, 6x86, K6 Clock Synthesizer/Driver for Desktop PCs with Intel 82430TX, 82440LX or ALI IV/IV+, AGP and 3 DIMMs |
| CY2273A-4 | 制造商:CYPRESS 制造商全称:Cypress Semiconductor 功能描述:Pentium㈢/II, 6x86, K6 Clock Synthesizer/Driver for Desktop PCs with Intel 82430TX, 82440LX or ALI IV/IV+, AGP and 3 DIMMs |
| CY2273APVC-1 | 制造商:Cypress Semiconductor 功能描述: |
| CY2273APVC-1T | 制造商:未知厂家 制造商全称:未知厂家 功能描述:CPU System Clock Generator |
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