参数资料
型号: CY2273A-4
厂商: Cypress Semiconductor Corp.
英文描述: Pentium㈢/II, 6x86, K6 Clock Synthesizer/Driver for Desktop PCs with Intel 82430TX, 82440LX or ALI IV/IV+, AGP and 3 DIMMs
中文描述: 奔腾㈢/ 2,6x86,K6时钟合成器/与英特尔82430TX,82440LX或阿里四/四,AGP和3个DIMM台式机驱动
文件页数: 4/14页
文件大小: 178K
代理商: CY2273A-4
CY2273A
4
Output impedance: 25
(typical) measured at 1.5V
Serial Configuration Map
The Serial bits will be read by the clock driver in the following
order:
Byte 0 - Bits 7, 6, 5, 4, 3, 2, 1, 0
Byte 1 - Bits 7, 6, 5, 4, 3, 2, 1, 0
.
.
Byte N - Bits 7, 6, 5, 4, 3, 2, 1, 0
Reserved and unused bits should be programmed to “0”.
I
2
C Address for the CY2273 is:
Actual Clock Frequency Values
Clock Output
Target
Frequency
(MHz)
Actual
Frequency
(MHz)
PPM
CPUCLK
66.67
66.654
–195
CPUCLK
60.0
60.0
0
CPUCLK
75.0
75.0
0
CPUCLK
83.33
83.138
–1947
USBCLK
48.0
48.008
167
Power Management Logic
[3]
- Active when MODE pin is held ‘LOW’
CPU_STOP
X
PCI_STOP
X
PWR_DWN
0
CPUCLK
Low
PCICLK
PCICLK_F
Stopped
Other
Clocks
Stopped
Osc.
Off
PLLs
Off
Low
0
0
1
Low
Low
Running
Running
Running
Running
0
1
1
Low
33/30 MHz
Running
Running
Running
Running
1
0
1
60/66/75/83 MHz
Low
Running
Running
Running
Running
1
1
1
60/66/75/83 MHz
30/33/30/33 MHz
Running
Running
Running
Running
A6
1
A5
1
A4
0
A3
1
A2
0
A1
0
A0
1
R/W
----
Byte 0: Functional and Frequency Select Clock
Register (1 = Enable, 0 = Disable)
Bit
Pin #
Description
Bit 7
--
(Reserved) drive to ‘0’
Bit 6
--
(Reserved) drive to ‘0’
Bit 5
--
(Reserved) drive to ‘0’
Bit 4
--
(Reserved) drive to ‘0’
Bit 3
--
(Reserved) drive to ‘0’
Bit 2
--
(Reserved) drive to ‘0’
Bit 1
Bit 0
--
Bit 1
1
1
0
0
Bit 0
1 - Three-State
0 - N/A
1 - Testmode
0 - Normal Operation
Select Functions
Functional Description
Outputs
SDRAM
-2 only
AGP
CPU
PCI, PCI_F
Ref
IOAPIC
USBCLK
Three-State
Test Mode
[5]
Hi-Z
TCLK/2
[4]
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
TCLK/4
TCLK/2
TCLK
TCLK
TCLK/2
TCLK/2
Notes:
3.
AGP clocks are driven on PCICLK5 and PCICLK4 on -2 option. These clocks behave similar to the PCICLK_F output, in that they are free-running and stop
only when the PWR_DWN pin is asserted. The frequency of the AGP clocks is as shown in the Function Table.
TCLK supplied on the XTALIN pin in Test Mode.
Valid only for SEL1=0.
4.
5.
相关PDF资料
PDF描述
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