参数资料
型号: CY22K7
厂商: Cypress Semiconductor Corp.
英文描述: 133-MHz Spread Spectrum Clock Generator For Use With the AMD-K7 Processor and AMD-750 Chipset
中文描述: 133 - MHz的扩频时钟发生器使用AMD - k7的处理器和AMD使用- 750芯片组
文件页数: 1/11页
文件大小: 141K
代理商: CY22K7
133-MHz Spread Spectrum Clock Generator For Use With
the AMD-K7
Processor and AMD-750 Chipset
CY22K7
Cypress Semiconductor Corporation
3901 North First Street
San Jose
CA 95134
408-943-2600
August 9, 1999
Features
Benefits
Multiple output clocks running at different frequencies
—Three open-drain differential CPU outputs running up
to 133 MHz
—Eight 3.3V synchronous PCI clocks (one free running)
—Two 3.3V AGP clocks at 2xPCI
—One dedicated 3.3V USB clock at 48 MHz
—One 3.3V USB/IO clock at 48 MHz or 24 MHz, selectable
via power-on latch input
—One 3.3V SDRAM clock output running at the CPU fre-
quency
—Two 3.3V Reference clocks at 14.318 MHz
Main clock generator for PC motherboard designs using the
AMD-K7 processor and AMD-750 Chipset
—Supports up to two CPUs and chipset
—Support for 4 PCI slots and chipset
—Supports designs using AGP
—Supports designs using USB
—Allows for one additional USB output or support for I/O
chip from various vendors
—Supports SDRAM memory architecture with external
PLL buffer
—Supports ISA slots and I/O chip
EMI reduction
Spread Spectrum clocking
—33 kHz modulation frequency
0.6% downspread margin
Dedicated inputs for various functions
— PCI_STOP
— CPU_STOP
— PWR_DWN
— SPREAD
— TEST
— USB/IO
— FS [0:1]
I
2
C interface
48-Pin SSOP package
Provides system design flexibility and power management
—Stops all PCI clocks (except PCICLK_F0) when LOW
—Stops all CPU clocks when LOW
—Power is removed from internal logic when LOW
—Activates Spread Spectrum for lower EMI
—Used to enter Test Mode
—Selects USB or SuperIO Clock
—Power-on latched inputs for frequency select options
Dynamic control of output clock signals via SMBus
Industry-standard package provides cost and space savings
Logic Block Diagram
14.318 MHz
Xtal
Oscillator
CPU PLL
STOP
LOGIC
STOP
LOGIC
DIVIDER
2X
/2
LATCH
SYSTEM PLL
CONTROL
LOGIC
XTALIN
XTALOUT
CPU_STOP
SPREAD
FSO
FS1
TEST
SCLK
SDATA
PCI_STOP
REF [0:1]
SDRAM_OUT
CPUCLKT [0:2]
CPUCLKC [0:2]
AGPCLK [0:1]
PCICLK [0:6]
PCICLK_F
USB0
USB/IO
PWR_DWN
USB/IO
相关PDF资料
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