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参数资料
| 型号： | CY2308SC-1H |
| 厂商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分类： | 时钟及定时 |
| 英文描述： | 3.3V Zero Delay Buffer |
| 中文描述： | 2308 SERIES, PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO16 |
| 封装： | 0.150 INCH, MS-012, SOIC-16 |
| 文件页数： | 1/15页 |
| 文件大小： | 371K |
| 代理商： | CY2308SC-1H |
CY2308
3.3V Zero Delay Buffer
Cypress Semiconductor Corporation
198 Champion Court
San Jose
, CA 95134-1709
408-943-2600
Document Number: 38-07146 Rev. *H
Revised March 12, 2009
Features
■ Zero input-output propagation delay, adjustable by capacitive
load on FBK input
■ Multiple configurations, see Available CY2308 Configurations
■ Multiple low skew outputs
■ Two banks of four outputs, three-stateable by two select inputs
■ 10 MHz to 133 MHz operating range
■ 75 ps typical cycle-to-cycle jitter (15 pF, 66 MHz)
■ Space saving 16-pin 150 mil SOIC package or 16-pin TSSOP
■ 3.3V operation
■ Industrial temperature available
Functional Description
The CY2308 is a 3.3V Zero Delay Buffer designed to distribute
high speed clocks in PC, workstation, datacom, telecom, and
other high performance applications.
The part has an on-chip PLL that locks to an input clock
presented on the REF pin. The PLL feedback is driven into the
FBK pin and obtained from one of the outputs. The
input-to-output skew is less than 350 ps and output-to-output
skew is less than 200 ps.
The CY2308 has two banks of four outputs each that is controlled
by the select inputs as shown in the table Select Input Decoding
on page 2. If all output clocks are not required, Bank B is
three-stated. The input clock is directly applied to the output for
chip and system testing purposes by the select inputs.
The CY2308 PLL enters a power down state when there are no
rising edges on the REF input. In this mode, all outputs are
three-stated and the PLL is turned off resulting in less than 50
μA
of current draw. The PLL shuts down in two additional cases as
shown in the table Select Input Decoding on page 2.
Multiple CY2308 devices accept the same input clock and
distribute it in a system. In this case, the skew between the
outputs of two devices is less than 700 ps.
The CY2308 is available in five different configurations as shown
in the table Available CY2308 Configurations on page 3. The
CY2308–1 is the base part where the output frequencies equal
the reference if there is no counter in the feedback path. The
CY2308–1H is the high drive version of the –1 and rise and fall
times on this device are much faster.
The CY2308–2 enables the user to obtain 2X and 1X frequencies
on each output bank. The exact configuration and output
frequencies depend on the output that drives the feedback pin.
The CY2308–3 enables the user to obtain 4X and 2X frequencies
on the outputs.
The CY2308–4 enables the user to obtain 2X clocks on all
outputs. Thus, the part is extremely versatile and is used in a
variety of applications.
The CY2308–5H is a high drive version with REF/2 on both
banks.
REF
CLKA1
CLKA2
CLKA3
CLKA4
FBK
PLL
MUX
Select Input
Decoding
S2
S1
CLKB1
CLKB2
CLKB3
CLKB4
/2
Extra Divider (–2, –3)
/2
Extra Divider (–3, –4)
Extra Divider (–5H)
/2
Logic Block Diagram
相关PDF资料 |
PDF描述 |
|---|---|
| CY2308SC-2 | AC 5C 2#16 1#12 2#4 PIN PLUG |
| CY2308SC-3 | 3.3V Zero Delay Buffer |
| CY2308SC-4 | 3.3V Zero Delay Buffer |
| CY2308SI-1 | 3.3V Zero Delay Buffer |
| CY2308SC-5H | 3.3V Zero Delay Buffer |
相关代理商/技术参数 |
参数描述 |
|---|---|
| CY2308SC-1HT | 功能描述:时钟缓冲器 3. 3V ZDB Internal Feedck RoHS:否 制造商:Texas Instruments 输出端数量:5 最大输入频率:40 MHz 传播延迟（最大值）: 电源电压-最大:3.45 V 电源电压-最小:2.375 V 最大功率耗散: 最大工作温度:+ 85 C 最小工作温度:- 40 C 封装 / 箱体:LLP-24 封装:Reel |
| CY2308SC1T | 制造商:CYPRESS 功能描述:NEW |
| CY2308SC-1T | 功能描述:时钟缓冲器 3. 3V ZDB Internal Feedck RoHS:否 制造商:Texas Instruments 输出端数量:5 最大输入频率:40 MHz 传播延迟（最大值）: 电源电压-最大:3.45 V 电源电压-最小:2.375 V 最大功率耗散: 最大工作温度:+ 85 C 最小工作温度:- 40 C 封装 / 箱体:LLP-24 封装:Reel |
| CY2308SC-2 | 功能描述:时钟缓冲器 3.3VZDB COM RoHS:否 制造商:Texas Instruments 输出端数量:5 最大输入频率:40 MHz 传播延迟（最大值）: 电源电压-最大:3.45 V 电源电压-最小:2.375 V 最大功率耗散: 最大工作温度:+ 85 C 最小工作温度:- 40 C 封装 / 箱体:LLP-24 封装:Reel |
| CY2308SC-2T | 制造商:Cypress Semiconductor 功能描述:Zero Delay PLL Clock Driver Single 10MHz to 133MHz 16-Pin SOIC T/R 制造商:Rochester Electronics LLC 功能描述:3.3 V ZERO DELAY BUFFER - Tape and Reel |
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